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Specification Update 9
Errata (Sheet 1 of 5)
Number
Steppings
Status ERRATA
C-0
HSD1
XNo Fix
LBR, BTS, BTM May Report a Wrong Address when an Exception/
Interrupt Occurs in 64-bit Mode
HSD2
XNo Fix
EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after
a Translation Change
HSD3
XNo Fix
MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a
DTLB Error
HSD4
XNo FixLER MSRs May Be Unreliable
HSD5
XNo Fix
MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in
Hang
HSD6
XNo Fix
An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also
Result in a System Hang
HSD7
XNo Fix
#GP on Segment Selector Descriptor that Straddles Canonical Boundary
May Not Provide Correct Exception Error Code
HSD8
XNo Fix
FREEZE_WHILE_SMM Does Not Prevent Event From Pending
PEBS During SMM
HSD9
XNo FixAPIC Error “Received Illegal Vector” May be Lost
HSD10
XNo Fix
Changing the Memory Type for an In-Use Page Translation May Lead to
Memory-Ordering Violations
HSD11
XNo Fix
Performance Monitor Precise Instruction Retired Event May Present
Wrong Indications
HSD12
XNo FixCR0.CD Is Ignored in VMX Operation
HSD13
XNo Fix
Instruction Fetch May Cause Machine Check if Page Size and Memory
Type Was Changed Without Invalidation
HSD14
XNo Fix
Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value
for VEX.vvvv May Produce a #NM Exception
HSD15
XNo FixProcessor May Fail to Acknowledge a TLP Request
HSD16
XNo Fix
Interrupt From Local APIC Timer May Not Be Detectable While Being
Delivered
HSD17
XNo Fix
PCIe* Root-port Initiated Compliance State Transmitter Equalization
Settings May be Incorrect
HSD18
XNo FixPCIe* Controller May Incorrectly Log Errors on Transition to RxL0s
HSD19
XNo FixUnused PCIe* Lanes May Report Correctable Errors
HSD20
XNo Fix
Accessing Physical Memory Space 0-640K through the Graphics
Aperture May Cause Unpredictable System Behavior
HSD21
XNo FixPCIe Root Port May Not Initiate Link Speed Change
HSD22
XNo Fix
Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than
Expected
HSD23
XNo Fix
DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP
SS is Followed by a Store or an MMX Instruction
HSD24
XNo FixVEX.L is Not Ignored with VCVT*2SI Instructions
HSD25
XNo Fix
Certain Local Memory Read / Load Retired PerfMon Events May
Undercount