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24 Specification Update
HSD24. VEX.L is Not Ignored with VCVT*2SI Instructions
Problem: The VEX.L bit should be ignored for the VCVTSS2SI, VCVTSD2SI, VCVTTSS2SI, and
VCVTTSD2SI instructions, however due to this erratum the VEX.L bit is not ignored and
will cause a #UD.
Implication: Unexpected #UDs will be seen when the VEX.L bit is set to 1 with VCVTSS2SI,
VCVTSD2SI, VCVTTSS2SI, and VCVTTSD2SI instructions.
Workaround: Software should ensure that the VEX.L bit is set to 0 for all scalar instructions.
Status: For the steppings affected, see the Summary Table of Changes.
HSD25. Certain Local Memory Read / Load Retired PerfMon Events May
Undercount
Problem: Due to this erratum, the Local Memory Read / Load Retired PerfMon events listed below
may undercount.
MEM_LOAD_RETIRED.L3_HIT
MEM_LOAD_RETIRED.L3_MISS
MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS
MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT
MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM
MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE
MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM
MEM_LOAD_L4_RETIRED.LOCAL_HIT
MEM_TRANS_RETIRED.LOAD_LATENCY
Implication: The affected events may undercount, resulting in inaccurate memory profiles. Intel has
observed u
ndercounts as much as 40%.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD26. Specific Graphics Blitter Instructions May Result in Unpredictable
Graphics Controller Behavior
Problem: Specific source-copy blitter instructions in Intel
®
HD Graphics 4600 Processor may
result in unpredictable behavior when a blit source and destination overlap.
Implication: Due to this erratum, the processor may exhibit unpredictable graphics controller
behavior. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD27. Processor May Enter Shutdown Unexpectedly on a Second
Uncorrectable Error
Problem: If an IA32_MCi_STATUS MSR contains an uncorrectable error with MCACOD=0x406 and
a second uncorrectable error occurs after warm reset but before the first error is
cleared by zeroing the IA32_MCi_STATUS MSR, a shutdown will occur.
Implication: When this erratum occurs, the processor will unexpectedly shut down instead of
executing the machine check handler.
Workaround: None identified. Software should clear IA32_MCi_STATUS MSRs as early as possible to
minimize the possibility of this erratum occurring.
Status: For the steppings affected, see the Summary Table of Changes.