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38 Specification Update
HSD82. PCIe* Host Bridge DID May Be Incorrect
Problem: The PCIe Host Bridge DID register (Bus 0; Device 0; Function 0; Offset 2H) contents
may be incorrect.
Implication: Software that depends on the Host Bridge DID value may not behave as expected.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD83. Transactional Abort May Produce an Incorrect Branch Record
Problem: If an Intel
®
TSX transactional abort event occurs during a string instruction, the From-
IP in the LBR (Last Branch Record) is not correctly reported.
Implication: Due to this erratum, an incorrect From-IP on the LBR stack may be observed.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD84. SMRAM State-Save Area Above the 4GB Boundary May Cause
Unpredictable System Behavior
Problem: If BIOS uses the RSM instruction to load the SMBASE register with a value that would
cause any part of the SMRAM state-save area to have an address above 4-GBytes,
subsequent transitions into and out of SMM (system-management mode) might save
and restore processor state from incorrect addresses.
Implication: This erratum may cause unpredictable system behavior. Intel has not observed this
erratum with any commercially available system.
Workaround: Ensure that the SMRAM state-save area is located entirely below the 4GB address
boundary.
Status: For the steppings affected, see the Summary Table of Changes.
HSD85. DMA Remapping Faults for the Graphics VT-d Unit May Not Properly
Report Type of Faulted Request
Problem: When a fault occurs during DMA remapping of Graphics accesses at the Graphics VT-d
unit, the type of faulted request (read or write) should be reported in bit 126 of the
FRCD_REG register in the remapping hardware memory map register set. Due to this
erratum, the request type may not be reported correctly.
Implication: Software processing the DMA remapping faults may not be able to determine the type
of faulting graphics device DMA request.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD86. AVX Gather Instructions Page Faults May Report an Incorrect Faulting
Address
Problem: If software modifies a paging-structure entry to relax the access rights for a linear address
and does not perform a TLB invalidation, a subsequent execution of an AVX gather
instruction that accesses that address may generate a page fault that loads CR2 (which
should containing the faulting linear address) with an incorrect value.
Implication: Software handling an affected page fault may not operate correctly.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.