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A Detailed Look Inside the Intel
®
NetBurst
™
Micro-Architecture of the Intel Pentium
®
4 Processor
Page 7
computations to operate on packed double-precision floating-point data elements and 128-bit packed integers. There
are 144 instructions in the SSE2 that can operate on two packed double-precision floating-point data elements, or on
16 packed byte, 8 packed word, 4 doubleword, and 2 quadword integers.
The full set of IA-32 SIMD technologies (the Intel MMX technology, the SSE extensions, and the SSE2 extensions)
gives the programmer the ability to develop algorithms that can combine operations on packed 64- and 128-bit
integer and single and double-precision floating-point operands.
This SIMD capability improves the performance of 3D graphics, speech recognition, image processing, scientific,
and other multimedia applications that have the following characteristics:
§ inherently parallel
§ regular and recurring memory access patterns
§ localized recurring operations performed on the data
§ data-independent control flow.
The IA-32 SIMD floating-point instructions fully support the IEEE* Standard 754 for Binary Floating-Point
Arithmetic. All SIMD instructions are accessible from all IA-32 execution modes: protected mode, real address
mode, and Virtual 8086 mode.
The SSE2 and SSE extensions, and the Intel MMX technology are architectural extensions in the IA-32 Intel
®
architecture. All existing software continues to run correctly, without modification, on IA-32 microprocessors that
incorporate these technologies. Existing software also runs correctly in the presence of new applications that
incorporate these SIMD technologies.
The SSE and SSE2 instruction sets also introduced a set of cacheability and memory ordering instructions that can
improve cache usage and application performance.
For more information on SSE2 instructions, including the cacheability and memory operation instructions, refer to
the IA-32 Intel
®
Architecture Software Developer’s Manual, Volume 1, Chapter 11 and Volume 2, Chapter 3, which
are available at: http://developer.intel.com/design/pentium4/manuals/.
Summary of SIMD Technologies
The paragraphs below summarize the new features of the three SIMD technologies (MMX technology, SSE, and
SSE2) that have been added to the IA-32 architecture in chronological order.
MMX Technology
§ Introduces 64-bit MMX registers.
§ Introduces support for SIMD operations on packed byte, word, and doubleword integers.
The MMX instructions are useful for multimedia and communications software.
For more information on the MMX technology, refer to the IA-32 Intel
®
Architecture Software Developer’s Manual,
Volume 1, available at http://developer.intel.com/design/pentium4/manuals/.
Streaming SIMD Extensions
§ Introduces 128-bit XMM registers.
§ Introduces 128-bit data type with four packed single-precision floating-point operands.
§ Introduces data prefetch instructions.
§ Introduces non-temporal store instructions and other cacheability and memory ordering instructions.
§ Adds extra 64-bit SIMD integer support.