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APPENDIX D
PCI-1712/1712L User’s Manual
Advantech Co., Ltd.
www.advantech.com
D. 9 Interrupt and FIFO status — Read BASE+8
Table D-9: Register for interrupt and FIFO status
INT_F Interrupt flag
This bit indicates whether interrupt occurred or not.
1 means that an interrupt has occurred.
A/D_F/E A/D FIFO empty flag
This bit indicates the A/D FIFO empty status
1 means A/D FIFO empty.
A/D_F/H A/D FIFO half-full flag
This bit indicates the A/D FIFO half-full status
1 means A/D FIFO halt-full.
A/D_F/F A/D FIFO full flag
This bit indicates the A/D FIFO full status
1 means A/D FIFO full.
D/A_F/E D/A FIFO empty flag
This bit indicates the D/A FIFO empty status
1 means D/A FIFO empty.
D/A_F/H D/A FIFO half-full flag
This bit indicates the D/A FIFO half-full status
1 means D/A FIFO halt-full.
D/A_F/F D/A FIFO full flag
This bit indicates the D/A FIFO full status
1 means D/A FIFO full.
.ddAesaB 51 41 31 21 11 01 9 8 7 6 5 4 3 2 1 0
8 R
sutatsOFIFdnatpurretnI
_A/D
F/F
_A/D
H/F
_A/D
E/F
_D/A
F/F
_D/A
H/F
_D/A
E/F
_TNI
F