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304-C03
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DX660 DMD BD
112Wednesday, April 17,2002
BILL WJ CHANG H.C.TSOU
48.J3401.S03 FAB:S03
ANGEL HU
99.J3477.001
A3
Title
SizeDocument Number Rev
Date: Sheet of
Project Code
Reviewed By ApprovedByPrepared By
120PIN_Connector&Peripherals
01_120PIN_Connector&Peripherals
LAMPEN
POWERON
CWINDEX
LAMPLIT
LAMPSYNC
CWSPEED
OPDIODE
SYNCVALID
U5_Relateds
02_U5_Relateds
CWINDEX
RESETZ
LAMPLIT
POWERON
LAMPEN
VSYNCZ
SR16STRO
SR16ADR0
SR16ADR1
SR16ADR2
SR16ADR3
SR16SEL0
SR16SEL1
SR16MOD0
SR16MOD1
VNEGSEN
SR16VCCE
DMDVCCEN
BINEEN
BINDEN
BINCEN
BINBEN
VCC2EN
VPBSEN
P3P3V
PLLRSTZ
SYSRSTZ
MWCMD1
MWCMD0
MRCMD0
MRCMD1
MRSEL12Z
MOENZ
DSTART
DWSCBD
MALSYNC
CTMRDY
MSMPLE
WSMPL
FPGADCLK
TFIELD
TCK
TMS
FPGA_TDO
LAMPSYNC
SYNCVALID
Flash
03_Flash
P3P3V
CPU&MotorDriver
04_CPU&MotorDriver
VDD
P12V
PBCLKZ
PBDATA1
PBDATA0
PBIRQ
DPF2A
05_DPF2A
PBCLKZ
PBDATA0
PBDATA1
SDDA[0..31]
SDDB[0..31]
SDA_MCLK
SDB_MCLK
SDA_MCSZ
SDB_MCSZ
DD[0:63]
DMD_DCLK
P3P3V
VDD
PLLRSTZ
SYSRSTZ
MWCMD1
MWCMD0
MRCMD0
MRCMD1
MRSEL12Z
MOENZ
DSTART
DWSCBD
MALSYNC
CTMRDY
MSMPLE
WSMPL
FPGADCLK
TFIELD
TCK
TMS
FPGA_TDO
PBIRQ
SDRAM
06_SDRAM
SDDA[0..31]
SDDB[0..31]
SDA_MCLK
SDB_MCLK
SDA_MCSZ
SDB_MCSZ
P3P3V
RESET_Device_A
07_RESET_Device_A
VDD
P12V
VNEGRAIL
VPOSRAIL
RESET_Device_B
08_RESET_Device
VNEGRAIL
SR16CVCC
DMDVCC
VRST
DMDVCCEN
SR16VCCE
VNEGSEN
VDD
RESET_Device_C
09_RESET_Device_C
VPOSRAIL
VBIAS
VCC2
VPBSEN
VCC2EN
BINBEN
BINCEN
BINDEN
BINEEN
P12V
KSR16C
10_KSR16C
SR16ADR0
SR16ADR1
SR16ADR2
SR16ADR3
SR16SEL0
SR16SEL1
SR16MOD0
SR16MOD1
SR16STRO
MBRST[0:14]
SR16CVCC
VRST
VCC2
VBIAS
80_Pin_Conn*2
11_80_Pin_Conn_2
MBRST[0:14]
DMDVCC
VCC2
VBIAS
LOAD16
UROWENZ
DMDACLK
DMDMODE0
DMDMODE1
COMP
LSET
LOADZ
SAC_BUS
DMD_DCLK
DD[0:63]
CWCTR
CWY1
CWY2
CWY3
VRST
VRST
DMDVCC
VBIAS
VCC2
DMDVCC
LSET
DMDMODE1
DMDMODE0
LOAD16
UROWENZ
LOADZ
COMP
DMDACLK
SAC_BUS
SR16ADR0
SR16ADR1
SR16ADR2
SR16ADR3
SR16SEL1
SR16SEL0
SR16MOD0
SR16MOD1
SR16STRO
DMDVCCEN
SR16VCCE
VNEGSEN
VPBSEN
VCC2EN
BINBEN
BINCEN
BINDEN
BINEEN
PBCLKZ
PBDATA1
VBIAS
VCC2
PBDATA0
VPOSRAIL
VCC2
VBIAS
VNEGRAIL
POWERON
LAMPEN
LAMPSYNC
LAMPLIT
CWINDEX
RESETZ
PBIRQ
PBIRQ
MBRST0
MBRST7
MOENZ
MWCMD1
SDDA[0..31]
PBDATA1
TFIELD
SDDB[0..31]
PBCLKZ
PLLRSTZ
PBCLKZ
PBIRQ
MWCMD0
MRSEL12Z
DMD_DCLK
FPGADCLK
SDA_MCLK
TMS
CTMRDY
MSMPLE
MRCMD1
WSMPL
DD[0:63] DD[0:63] DD[0:63]
SDA_MCSZ
SYSRSTZ
PBDATA0
VSYNCZ
PBDATA0
MALSYNC
SDB_MCLK
DMD_DCLK DMD_DCLK
MRCMD0
DSTART
PBDATA1
FPGA_TDO
TCK
SDB_MCSZ
DWSCBD
OPDIODE
CWSPEED
CWCTR
CWY1
CWY2
CWY3
SYNCVALID
P12V VDD P3P3V
VDDP3P3V
VDDP12V
P3P3V
P3P3V
VDDP12VP12V
P3P3V
VDD
TP18
E1
TP2
E1
TP5E1
1
TP11
E1
TP17
E1
1
TP4
E1
TP14
E1
TP20
E1
1
TP10
E1
TP16
E1
1
TP23
E1
1
TP3
E1
TP6
E1
1
TP19
E1
1
TP9
E1
TP12
E1
TP1
E1
TP15
E1
TP22
E1
1
TP7
E1
1
TP13
E1
TP8
E1
TP21
E1
1