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Operational Environment 3-5
Copyright © 2001 by LSI Logic Corporation. All rights reserved.
Table 3.2 PCI Connector J1 (Front)
1
1. Shaded lines are not connected.
Signal Name Pin Signal Name Pin
−12 V 1 AD17 32
TCK 2 C_BE2
2
2. Active LOW signal.
33
GND 3 GND 34
TDO 4 IRDY
2
35
+5 V 5 +3.3 V 36
+5 V 6 DEVSEL
2
37
INTB
2
7 GND
2
38
INTD
2
8 LOCK
2
39
GND(PRSNT1
2
) 9 PERR
2
40
RESERVED 10 +3.3 V 41
GND(PRSNT2
2
) 11 SERR
2
42
KEYWAY 12 +3.3 V 43
KEYWAY 13 C_BE1
2
44
RESERVED 14 AD14 45
GND 15 GND 46
CLK 16 AD12 47
GND 17 AD10 48
REQ
2
18 M66EN (LVD) 49
3 V/5 V 19 KEYWAY 50
AD31 20 KEYWAY 51
AD29 21 AD08 52
GND 22 AD07 53
AD27 23 +3.3 V 54
AD25 24 AD05 55
+3.3 V 25 AD03 56
C_BE3
2
26 GND 57
AD23 27 AD01 58
GND 28 3 V/5 V 59
AD21 29
ACK64
2
60
AD19 30 +5 V 61
+3.3 V 31 +5 V 62