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PCI-QUAD-AC5 User's Guide Introducing the PCI-QUAD-AC5
Block Diagram
PCI-QUAD-AC5 functions are illustrated in the block diagram shown here.
PCI
Controller
BADR2
Boot
EEPROM
Decode/Status
Bus
Timing
Controller FPGA and Logic
Local Bus
PCI Bus (5V, 32-BIT, 33MHZ)
Control
Bus
Port A
Port B
Control
A(7:0)
B(7:0)
Port C
C(7:0)
S
S
R
-
P
B
2
4
AC/DC
Port A
Port B
Control
A(7:0)
B(7:0)
Port C
C(7:0)
S
S
R
-
P
B
2
4
AC/DC
I/O Module
Racks
Port A
Port B
Control
A(7:0)
B(7:0)
Port C
C(7:0)
S
S
R
-
P
B
2
4
AC/DC
Port A
Port B
Control
A(7:0)
B(7:0)
Port C
C(7:0)
S
S
R
-
P
B
2
4
AC/DC
I/O Module
Racks
1-2