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Chapter 4 Functional Overview
7344/7334 Hardware User Manual 4-6 ni.com
Host Communications
The host computer communicates with a 7344/7334 controller through a
number of memory port addresses on the host bus. The host bus can be any
of the supported bus standards—PCI, PXI, or 1394.
The primary bidirectional data transfer port is at the base address of the
controller. This port supports FIFO data passing in both send and readback
directions. The 7344/7334 controller has both a command buffer for
incoming commands and a return data buffer (RDB) for readback data.
At address offsets from the base address are two read-only status registers.
The communications status register (CSR) provides bits for
communications handshaking as well as real-time error reporting and
general status feedback to the host PC. The move complete status (MCS)
register provides instantaneous motion status of all axes.