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Chapter 2 NI SPEEDY-33 Functional Description and Interface
NI SPEEDY-33 User Manual 2-2 ni.com
DSP
The digital signal processor on the NI SPEEDY-33 is a powerful
floating-point, flexible, and easy-to-use processor designed by Texas
Instruments.
The VC33 DSP is capable of high performance mathematical operations.
It is a 32-bit, floating-point processor manufactured in 0.18 μm
four-level-metal CMOS (TImeline™) technology, and is part of the
SM320C3x
™
generation of DSPs from Texas Instruments.
The VC33 DSP internal busing and special digital signal processing
instruction set have the speed and flexibility to execute up to 150 million
floating-point operations per second (MFLOPS). The VC33 DSP optimizes
speed by implementing functions in hardware that other processors
implement through software or microcode. This hardware-intensive
approach provides performance previously unavailable on a single chip.
Note Although this DSP is capable of 75 MIPS, 150 MFLOPS, the crystal driving the
DSP on the NI SPEEDY-33 is slightly slower than what would be required to achieve this
maximum speed, namely 14.7456 MHz as opposed to the maximum 15 MHz. This allows
for specific desirable sample rates to be achieved for the A/D and D/A hardware described
in the Stereo A/D, D/A (Analog Input, Analog Output) section. Refer to the Appendix A,
Specifications, for information about DSP speed.
The VC33 DSP can perform parallel multiply and ALU operations on
integer or floating-point data in a single cycle. Each processor possesses a
general-purpose register file, a program cache, dedicated ARAUs, internal
dual-access memories, one DMA channel supporting concurrent I/O, and a
short machine-cycle time, resulting in a high-performance, easy-to-use
device.
Typical signal processing applications are enhanced by the large address
space, multiprocessor interface, internally- and externally-generated wait
states, one external interface port, two timers, one serial port, and a
multiple-interrupt structure. The VC33 DSP supports a wide variety of
system applications from host processor to dedicated coprocessor.
High-level language support is easily implemented through a register-based
architecture, large address space, powerful addressing modes, flexible
instruction set, and well-supported floating-point arithmetic.