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The following tables summarizes all possible Offset/Range configurations
:
PCI-DAS1002
305 uV8
0-1.25V
111
610 uV4
0-2.5V
011
1.22 mV2
0-5V
101
2.44 mV1
0-10V
001
610 uV8
±1.25V
110
1.22 mV4
±2.5V
010
2.44 mV2
±
5V
100
4.88 mV1
±10V
000
Measurement
Resolution
Input GainInput RangeGS0GS1UNIBIP
PCI-DAS1001
2.44 uV1,000
0-0.01V
111
24.4 uV100
0-0.1V
011
244 uV10
0-1V
101
2.44 mV1
0-10V
001
4.88 uV1,000
±0.01V
110
48.8 uV100
±0.1V
010
488 uV10
±
1V
100
4.88 mV1
±10V
000
Measurement
Resolution
Input GainInput RangeGS0GS1UNIBIP
ADPS[1:0]
These bits select the ADC Pacer Source. Maximum Internal/External Pacer
frequency is 330KHz.
External Rising11
External Falling01
82C54 Counter/Timer10
SW Convert00
Pacer SourceADPS0ADPS1
Note: For ADPS[1:0] = 00 case, SW conversions are initiated
via a word write to BADR2 + 0. Data is 'don't care.'
READ
--------------EOC-
0123456789101112131415
EOC
Real-time, non-latched status of ADC End-of-Conversion signal.
1 = ADC DONE
0 = ADC BUSY
20