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Quatech, Inc. Airborne Enterprise Module Databook
22 8/11/2009 100-8080-110
7.0 SPI Interface
The following section details the SPI interface specification for both hardware timing and
SPI protocol. The device is a SPI slave and requires a compatible SPI master for
operation.
7.1 Pinout
When the SPI interface is enabled, through the CLI or web interface, the
following pins are assigned for communication.
Table 11 - SPI Pinout Details
Pin Definition
SPI
UART2 Pin
Debug
Master In Slave Out (MISO)
28
Master Out Slave In (MOSI)
24
SPI Interrupt (SPI_INT)
22
SPI Clock (SPI_CLK)
18
SPI Select (/SPI_SEL)
12
Data In (RxD2, DTXD)
9
8
Data out (TxD2, DRXD)
21
6
Ready-to-Send (RTS2)
17
Clear-to-Send (CTS2)
19
Table 12 - SPI Signal Descriptions
Pin Definition
Description
Master In Slave Out (MISO)
Serial Data OUT; must be connected to the serial data in of
the master.
Master Out Slave In (MOSI)
Serial Data IN; Must be connected to the serial data out of the
master.
SPI Interrupt (SPI_INT)
Interrupt signal driver by slave see Table 16 for details of
operation.
SPI Clock (SPI_CLK)
SPI clock sourced from the master.
SPI Select (/SPI_SEL)
Enable the SPI slave, sourced from the master. Active low
signal.
7.2 SPI AC Characteristics
The following specification identifies the required hardware timing to successfully
implement a SPI interface with the Airborne Device Server module.