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S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS
9-7
PORT 1
Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading
the port 1 data register, P1 at location F1H in set 1, bank 0. P1.0−P1.7 can serve as inputs (with or without pull-
up), as outputs (push-pull or open-drain) or you can be configured the following functions.
• Low-nibble pins (P1.0−P1.3): SCK, SO, SI, INT3
• High-nibble pins (P1.4−P1.7): INT4−INT7
Port 1 Control Registers (P1CONH, P1CONL)
Port 1 has two 8-bit control registers: P1CONH for P1.4−P1.7 and P1CONL for P1.0−P1.3. A reset clears the
P1CONH and P1CONL registers to "00H", configuring P1.3−P1.7 pins to input mode with interrupt and P1.0−P1.2
pins to input mode. You use control registers setting to select input or output mode (push-pull or open-drain) and
enable the alternative functions.
When programming this port, please remember that any alternative peripheral I/O function you configure using the
port 1 control registers must also be enabled in the associated peripheral module.
Port 1 Pull-up Resistor Control Register (P1PUR)
Using the port 1 pull-up resistor control register, P1PUR (E9H, set 1, bank 0), you can configure pull-up resistors
to individual port 1 pins.
Port 1 Interrupt Control Registers (EXTICONH, EXTICONL.7−.6, EXTIPND.7−.3)
To process external interrupts at the port 1 pins, three additional control registers are provided: the external
interrupt control registers EXTICONH/EXTICONL.7−.6 (F8H/F9H, set 1, bank 0) and the external interrupt
pending register EXTIPND.7−.3 (F7H, set 1, bank 0).
The external interrupt pending register EXTIPND.7−.3 lets you check for interrupt pending conditions and clear
the pending condition when the interrupt service routine has been initiated. The application program detects
interrupt requests by polling the EXTIPND.7−.3 register at regular intervals.
When the interrupt enable bit of any port 1 pin is "1", a rising or falling edge at that pin will generate an interrupt
request. The corresponding pending bit is then automatically set to "1" and the IRQ level goes low to signal the
CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software
must the clear the pending condition by writing a "0" to the corresponding EXTIPND bit.