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BIOS Setup Utility
SY-7ISA+
68
CHIPSET FEATURES SETUP
CHIPSET
FEATURES
Setting Description Note
Disabled Default
System BIOS
Cacheable
Enabled The ROM area F0000H-FFFFFH is
cacheable.
Disabled Default
Video BIOS
Cacheable
Enabled The video BIOS C0000H-C7FFFH is
cacheable.
Disabled Default
Memory
Hole At
15M-16M
Enabled Some interface cards will map their
ROM address to this area. If this
occurs, select [Enabled] in this field.
Disabled
CPU Latency
Timer
Enabled
When enabled this item, the CPU
cycle will only be deferred after it has
been held in a “Snoop Stall” for 31
clocks and another ADS# has arrived.
When disabled, the CPU cycle will be
deferred immediately after the GMCH
receives another ADS#.
Default
Disabled
Delayed
Transaction
Enabled
The chipset has an embedded 32-bit
posted write buffer to support delay
transactions cycles. Select Enabled to
support compliance with PCI
specification version 2.1.
Default
64MB Default
AGP
Graphics
Aperture
Size
32MB
Select the size of Accelerated Graphics
Port (AGP) aperture. The aperture is a
portion of the PCI memory address
range dedicated for graphics memory
address space. Host cycles that hit
the aperture range are forwarded to the
AGP without any translation.
Disabled
Use VGA
BIOS in VBU
Block
Enabled
If you do not make use of the onboard
VGA function you can set this item to
disabled, this way the VGA BIOS will
not be copied into the bootblock.
Default