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LAN9118 Family Programmer Reference Guide
SMSC AN 12.12 9 Revision 1.0 (12-14-09)
APPLICATION NOTE
3.5 Restrictions on Read-Follow-Read CSR Accesses
There are also restrictions on certain CSR read operations following other read operations. These
restrictions arise when a read operation has a side-effect that affects another read operation. In many
cases there is a delay between reading the a CSR and the subsequent side-effect. To prevent the host
from reading invalid status, minimum wait periods have been established. These wait periods are
implemented by having the host perform “dummy” reads of the BYTE_TEST register. The required
dummy reads are listed in the Table 3.5 below:
Table 3.4 Read after Write Timing Rules
REGISTER NAME
MINIMUM WAIT AFTER ANY
WRITE CYCLE (IN NS)
NUMBER OF BYTE_TEST READS
(ASSUMING 45NS T
CYC)
ID_REV 0 0
INT_CFG 135 3
INT_STS 90 2
INT_EN 45 1
BYTE_TEST 0 0
FIFO_INT 45 1
RX_CFG 45 1
TX_CFG 45 1
HW_CFG 45 1
RX_DP_CTRL 45 1
RX_FIFO_INF 0 0
TX_FIFO_INF 135 3
PMT_CTRL 513 7
GPIO_CFG 45 1
GPT_CFG 45 1
GPT_CNT 135 3
WORD_SWAP 45 1
FREE_RUN 180 4
RX_DROP 0 0
MAC_CSR_CMD 45 1
MAC_CSR_DATA 45 1
AFC_CFG 45 1
E2P_CMD 45 1
E2P_DATA 45 1