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Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
Revision 1.0 (05-28-09) 18 SMSC LAN8720/LAN8720i
DATASHEET
Chapter 4 Architecture Details
4.1 Top Level Functional Architecture
Functionally, the transceiver can be divided into the following sections:
100Base-TX transmit and receive
10Base-T transmit and receive
RMII interface to the controller
Auto-negotiation to automatically determine the best speed and duplex possible
Management Control to read status registers and write control registers
4.2 100Base-TX Transmit
The data path of the 100Base-TX is shown in Figure 4.1. Each major block is explained below.
4.2.1 100M Transmit Data Across the MII/RMII Interface
For MII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate
valid data. The data is latched by the transceiver’s MII block on the rising edge of TXCLK. The data
is in the form of 4-bit wide 25MHz data.
For RMII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate
valid data. The data is latched by the transceiver’s RMII block on the rising edge of REF_CLK. The
data is in the form of 2-bit wide 50MHz data.
Figure 4.1 100Base-TX Data Path
MAC
Tx
Driver
MLT-3
Converter
NRZI
Converter
4B/5B
Encoder
CAT-5RJ45
25MHz by
5 bits
NRZI
MLT-3MLT-3
MLT-3
Scrambler
and PISO
RMII
25MHz
by 4 bits
Ref_CLK
PLL
RMII 50Mhz by 2 bits
MLT-3
Magnetics
125 Mbps Serial