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Super I/O with Temperature Sensing, Quiet Auto Fan and Glue Logic with PECI
Revision 0.2 (02-11-09) 4 SMSC SCH5027E
PRODUCT PREVIEW
Block Diagram
Figure 1 SCH5027E Block Diagram
LEDs
LED2*
LED1*
Internal Bus
(Data, Address, and Control lines)
Power Mgmt
IO_PME_S5*
IO_SMI*
GP1[0:4]*, GP21*,GP22*
GP27*, GP32*,GP33*
GP36*, GP37* , GP4[0,2,3]*
GP5[0:1]*, GP6[0:1]*
Note 1: This diagram does not show power and ground
connections.
Note 2: Signal names followed by an asterisk (*) are
located on multifunction pins. This diagram is designed to
show the various functions available on the chip and
should not be used as a pin layout.
CLOCK
GEN
CLK32
CLOCKI
WDT
32 byte
Security
Key
Register
nDSR1, nDTR1
nDCD1, nRI1
Power Control
and Recovery
`
SLP_S3#, SLP_S5#
PWRGD_CPU ,
PWRGD_3V
SLP_S3DEL#
PS_ON#
nRSMRST
nFPRST, PB_IN#
PWRGD_PS
nHWM_INT
VREF
PECI_REQUEST#*
PECI
READY
VID3/PWMA
VID4/PWMB
VID5 / FANTACH3
V1_IN
V2_IN
VCCP_IN
+2.5VTR_IN
Remote1-
Remote1+
Remote2-
Remote2+
PWM1/xTest Out
PWM2
PWM3/ ADDR_EN#
FANTACH1
FANTACH2
FANTACH4/ ADDR_SEL
PWMA*, PWMB*
FANTACHA*
FANTACHB*
S
M
B
u
s
SDA
SCLK
Hardware
Monitor
General
Purpose
I/O
IO_PME_S3*
VCC
VTR
Vbat
SLP_S3#
SLP_S5#
HWN_INT
14.318Mhz
96 Mhz
PCI_RESET#
WDT*
SER_IRQ
LAD[3:0]
LFrame#
LDRQ#
PCI_RESET#
PCI_CLK
LPC
Bus Interface
SERIAL
IRQ
SMbus
Isola-
tion
Switch
SDA1
SCLK1
SDA2
SCLK2
SMSC
Proprietary
82077
Compatible
Floppydisk
Controller with
Digital Data
Separator &
Write Precom-
pensation
nRDATA, nWDATA
nDIR, nSTEP
nMTR0, nTRK0, InNDEX
DRVDEN0*, nWRTPRT
nWGATE, nHDSEL
nDSKCHG, nDS0,
High-Speed
16550A
UART
PORT 1
TXD1*, RXD1
nCTS1, nRTS1*
Multi-Mode
Parallel Port
with
ChiProtect
TM
/
FDC MUX
(see LPC47B27x)
PD[7,0]
BUSY, SLCT, PE,
nERROR, nACK
nSTROBE, nINIT,
nSLCTIN, nALF
Intruder
Detection
nINTRD_IN
Keyboard/Mouse
8042
controller
KCLK*, KDAT*
MCLK*, MDAT*
A20M*
nKBDRST*
PCI Reset
Outputs
nPCIRST_OUT[1:4]*
nIDE_RSTDRV*
High-Speed
16550A
UART
PORT 2
TXD2 (IRTX)*,
RXD2 (IRRX)*
DSR2*, DTR2*
DCD2*, RI2*
CTS2*, RTS2 *