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SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache
UltraSPARC
™
-II CPU Module
July 1999
Sun Microsystems, Inc
UPAACTIMING SPECIFICATIONS
The UPA AC Timing Specifications are referenced to the UPA connector. The timing assumes that the clocks
are correctly distributed, (see the section "System Clock Distribution," on page 9). The effective PCB clock
trace lengths (CPU_CLK, UPA_CLK0 and UPA_CLK1) are used to calculate a balanced clock system.
UPA_CLK Module Clocks
All the UPA_CLKx trace pairs are the same length coming from the clock buffer and going to each load. To
calculate UPA_CLK0 and UPA_CLK1 for the module, assume the trace lengths on the module are 9 inches,
(which includes the module connector).
CPU_CLK Module Clock
The CPU_CLK trace on the system board is typically only a few inches long. It is the length of the traces used
for the UPA_CLKs from the clock buffer plus the length of UPA_CLK from the clock divider to the clock
buffer minus the effective trace length of CPU_CLK on the module, 18 inches, including the module
connector.
Clock Buffers
The Clock buffer on the systemboard and the clock buffer on the module are assumed to have similar delays.
The clock buffers have a 600 ps delay.
Timing References
The setup, hold and clock to output timing specifications are referenced at the module connector for the sig-
nal and at the system UPA device pin. There is no reference point associated with the module since the
module trace lengths provided above are effective lengths only and may not represent actual traces.
The following table specifies the AC timing parameters for the UPA bus. For waveform illustrations see the
illustration, "Timing Measurement Waveforms," on page 15.
Static signals consist of: UPA_PORT_ID[1:0], UPA_RATIO, and UPA_SPEED[2:0].
Setup and Hold Time Specifications
Symbol Setup Signals and Hold Time Signals Waveforms
400 MHz CPU
100 MHz UPA
UnitMin Max
t
SU
Setup time
UPA_DATA [127:0] 1 3.4 – ns
UPA_ADDR [35:0]
UPA_ADDR_VALID, UPA_REQ_IN [2:0],
UPA_SC_REQ_IN, UPA_DATA_STALL,
UPA_ECC_VALID, UPA_RESET_L, UPA_XIR_L
1 2.9 – ns
UPA_ECC [15:0] 1 3.4 – ns
UPA_S_REPLY [3:0] 1 3.4 – ns