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400 MHz CPU, 4.0 MB E-Cache
UltraSPARC
™
-II CPU Module
SME5224AUPA-400
Advanced Version
July 1999
Sun Microsystems, Inc
SIGNAL DESCRIPTION
[1]
System Interface
Signal Type Name and Function
UPA_ADDR[35:0] I/O Packet switched transaction request bus. Maximum of three other masters and one
system controller can be connected to this bus. Includes 1-bit odd-parity protection.
Synchronous to UPA_CLK.
UPA_ADDR_VALID I/O Bidirectional radial UltraSPARC-II Bussignalbetween theUltraSPARC-IICPU andthe
system. Driven by UltraSPARC-II to initiate UPA_ADDR transactions to the system.
Driven by system to initiate coherency, interrupt or slave transactions to
UltraSPARC-II CPU. Synchronous to UPA_CLK. Active high.
UPA_REQ_IN[2:0] I UltraSPARC-II system address bus arbitration request from up to three other
UltraSPARC-II bus ports, which may share the UPA_ADDR. Used by the
UltraSPARC-II for thedistributed UPA_ADDRarbitration protocol.Connection to other
UltraSPARC-II bus ports is strictly dependent on the Master ID allocation.
Synchronous to UPA_CLK. Active high.
UPA_SC_REQ_IN I UltraSPARC-II system address bus arbitration request from the system. Used by the
UltraSPARC-II CPU for the distributed UPA_ADDR arbitration protocol.
Synchronous to UPA_CLK. Active high.
UPA_S_REPLY[4:0] I UltraSPARC-II system reply packet, driven by system controller to the UPA port.
Synchronous to UPA_CLK. Active high. UPA_S_REPLY [4] is a no-connect.
UPA_DATA_STALL I Driven by system controller to indicate whether there is a data stall. Active high.
UPA_P_REPLY[4:0] O UltraSPARC-II system reply packet, driven by the UltraSPARC-II to the system.
Synchronous to UPA_CLK. Active high.
UPA_DATA[127:0] I/O UPA Interconnect data bus.
UPA_ECC[15:0] I/O ECC bits for the data bus. 8-bit ECC per 64-bits of data.
UPA_ECC_VALID I Driven by the system controller to indicate that the ECC is valid for the data on the
UPA interconnect data bus: active high.
UPA_REQ_OUT I/O Arbitration request from this module: active high.
UPA_PORT_ID[1:0] I Module’s identification signals: active high. UPA_SPEED[1] acts as a
UPA_PORT_ID[2]
1. For the modular connector pin assignments (UPA pin-out assignments) see page 24 and page 25.
Clock Interface
Signal Type Name and Function
UPA_CLK[1:0]_POS
UPA_CLK[1:0]_NEG
I UPA Interconnect Clock: two copies are provided, one for the CPU and one for the
UDBs
CPU_CLK_POS
CPU_CLK_NEG
I Differential Clock inputs to the clock buffer on the module
UPA_RATIO I This is not used.
UPA_SPEED [0] O UPA_SPEED [0] is an output tied low on the module
UPA_SPEED [1] I/O UPA_SPEED[1] is tied low with 510 ohms and high to 3.3V with 4.7k ohms. It is
also connected to the SYSID [2] on each UDB-II.
UPA_SPEED [2] O UPA_SPEED [2] is tied low on the module