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12
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Ult
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SPARC
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2
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Sun Microsystems, Inc.
Table 2 provides a comparison between the UltraSPARC T2 and the UltraSPARC T1
processor.
Table 2. UltraSPARC T1 and T2 processor features
Taking Chip Multithreaded Design to the Next Level
When Sun’s in-house design team set out to design the next-generation of CMT
processors, they started with key goals in mind:
• Increasing computational capabilities to meet the growing demand from Web
applications by providing twice the throughput of the UltraSPARC T1 processor
• Supporting larger and more diverse workloads with greater floating point
performance
• Powering faster networking to serve new network-intensive content
• Providing end-to-end datacenter encryption
• Increasing service levels and reducing downtime
• Improving datacenter capacities while reducing costs
CMT architecture is ultimately very flexible, allowing different modular combinations of
processors, cores, and integrated components. The considerations listed above drove
an internal engineering effort that compared different approaches with regard to
making improvements on the successful UltraSPARC T1 architecture. For example,
Feature UltraSPARC T1 Processor UltraSPARC T2 processor
Cores per processor
Up to 8 Up to 8
Threads per core
48
Threads per processor
32 64
Hypervisor
Yes Yes
Memory
4 memory controllers,
4 DIMMs per controller
4 memory controllers,
up to 64 FBDIMMs
Caches
16 KB instruction cache,
8 KB data cache,
3 MB L2 cache (4 banks,
12-way associative)
16 KB instruction cache,
8 KB data cache,
4 MB L2 cache (8 banks,
16-way associative)
Technology
9-layer Cu metal, CMOS
process, 90 nm technology
65 nm technology
Floating point
1 FPU per chip 1 FPU per core,
8 FPUs per chip
Integer resources
Single execution unit 2 integer execution units per
core
Cryptography
Accelerated modular
arithmetic operations (RSA)
Stream processing unit per
core, support for the 10 most
popular ciphers
Additional on-chip
resources
— Dual 10 Gb Ethernet
interfaces,
PCI Express interface (x8)