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B-5
Appendix B: AMIBIOS POST Diagnostic Error Messages
APPENDIX B
Check
Point Description
4C The memory below 1 MB has been cleared via a soft
reset. Clearing the memory above 1 MB next.
4D The memory above 1 MB has been cleared via a soft
reset. Saving the memory size next. Going to checkpoint
52h next.
4E The memory test started, but not as the result of a soft
reset. Displaying the first 64 KB memory size next.
4F The memory size display has started. The display is
updated during the memory test. Performing the
sequential and random memory test next.
50 The memory below 1 MB has been tested and
initialized. Adjusting the displayed memory size for
relocation and shadowing next.
51 The memory size display was adjusted for relocation
and shadowing. Testing the memory above 1 MB next.
52 The memory above 1 MB has been tested and
initialized. Saving the memory size information next.
53 The memory size information and the CPU registers are
saved. Entering real mode next.
54 Shutdown was successful. The CPU is in real mode.
Disabling the Gate A20 line, parity, and the NMI next.
57 The A20 address line, parity, and the NMI are
disabled. Adjusting the memory size depending on
relocation and shadowing next.
58 The memory size was adjusted for relocation and
shadowing. Clearing the Hit <DEL> message next.
59 The Hit <DEL> message is cleared. The <WAIT>
message is displayed. Starting the DMA and interrupt
controller test next.