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The following paragraphs describe the function of the individual circuits. See the data sheet for device operating characteristics.
3-3
Circuit Description
3.1.3 Clock Inputs
The EVM provides separate inputs for the ADC clock and output buffer clock.
This allows the user to send a modified version of the ADC clock (inverted,
delayed, etc.) with the output data to generate the required setup and hold
times for the user interface. The ADC clock input is SMA connector J3 and has
provisions for serial and/or parallel termination. The buffered output clock
input is SMA connector J4 and has provisions for serial and/or parallel
termination. The clock inputs must be 50-Ω square wave signals, 1.8-V or
3.3-V referenced to ground, with a duty cycle of 50 ±5%. The EVM can operate
with only one clock input by installing R43 and R44, and removing R41 and R8
to prevent double termination.
3.1.4 Control Inputs
The ADC has three discrete inputs to control the operation of the device.
3.1.4.1 Standby
With jumper W4 installed between pins 2 and 3, the ADC is in power-down
mode. The device is in operate mode with jumper W4 installed between pin 1
and pin 2.
3.1.4.2 Output Enable
With jumper W5 installed between pins 1 and 2, the ADC data outputs are in
a 3-state mode. The data outputs are enabled with jumper W5 installed
between pins 2 and 3.
3.1.4.3 Power Down Reference
With jumper W6 installed between pins 1 and 2, the ADC internal reference
is disabled and the device is in external reference mode. The ADC is in internal
reference mode with jumper W6 installed between pins 2 and 3.
3.1.5 Power
Power is supplied to the EVM via banana jack sockets. A separate connection
is provided for a 1.8-V analog supply (J6 and J5), a 1.8-V digital supply (J9 and
J10), a 1.8/3.3-V digital driver supply (J13 and J14), and a ±5-V analog supply
(J7, J8, and J11).
3.1.6 Outputs
The data outputs from the ADC are buffered using a SN74AVC16244 before
going to header J15. The ADC and output buffer can provide 1.8-V or 3.3-V
output levels. The voltage placed at the driver power inputs (J13 and J14)
selects this. J15 is a standard 40-pin header on a 100-mil grid, and allows easy
connection to a logic analyzer. The connector pin out is listed in Table 3–2.