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Appendices Apx. C Pin Assignments
C-26 Satellite A100/A105 / TECRA A7 Maintenance Manual
175 /M_DATA(51)'
I/O
176 /M_DATA(55)'
I/O
177 DGND'
-
178 DGND'
-
179 /M_DATA(56)'
I/O
180 /M_DATA(60)'
I/O
181 /M_DATA(57)'
I/O
182 /M_DATA(61)'
I/O
183 DGND'
-
184 DGND'
O
185 /M_DM(7)'
-
186 /M_DQS#(7)'
I/O
187 DGND'
-
188 /M_DQS(7)'
I/O
189 /M_DATA(58)'
I/O
190 DGND'
-
191 /M_DATA(59)'
I/O
192 /M_DATA(62)'
I/O
193 DGND'
-
194 /M_DATA(63)'
I/O
195 /SB_SMDAT_3'
I/O
196 DGND'
-
197 /SB_SMCLK_3'
I/O
198 /N$837418'
-
199 /+V3S'
-
200 /N$837419'
-
C.33 CN508 DDR2 DIMM1 Socket (200-Pin)
Table C-33 DDR2 DIMM1 Socket pin assignments (200-Pin)
Pin No. Signal Name I/O Pin No. Signal Name I/O
1 /SM_VREF'
I/O
2 DGND'
-
3 DGND'
-
4 /M_DATA(4)'
I
5 /M_DATA(0)'
I/O
6 /M_DATA(5)'
I/O-
7 /M_DATA(1)'
I/O
8 DGND'
-
9 DGND'
-
10 /M_DM(0)'
-
11 /M_DQS#(0)'
O
12 DGND'
-
13 /M_DQS(0)'
I/O
14 /M_DATA(6)'
I/O
15 DGND'
-
16 /M_DATA(7)'
-
17 /M_DATA(2)'
I/O
18 DGND'
I/O
19 /M_DATA(3)'
I/O
20 /M_DATA(12)'
I/O
21 DGND'
-
22 /M_DATA(13)'
I/O
23 /M_DATA(8)'
I/O
24 DGND'
-
25 /M_DATA(9)'
O
26 /M_DM(1)'
O
27 DGND'
-
28 DGND'
-
29 /M_DQS#(1)'
I/O
30 /M_CLK_DDR1'
I/O
31 /M_DQS(1)'
I/O
32 /M_CLK_DDR1#'
I/O
33 DGND'
-
34 DGND'
-