AMD 10 Computer Hardware User Manual


 
2 Overview Chapter 1
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004
The AMD Sempron processor model 10 with 256K of L2 cache is
binary-compatible with existing x86 software and backwards
compatible with applications optimized for MMX™, SSE, and
3DNow!™ technology. Using a data format and
single-instruction multiple-data (SIMD) operation based on the
MMX instruction model, the AMD
Sempron processor model 10
can produce as many as four, 32-bit, single-precision
floating-point results per clock cycle. The 3DNow! Professional
technology implemented in the AMD Sempron processor model
10 with 256K of L2 cache includes integer multimedia
instructions and software-directed data movement instructions
for optimizing such applications as digital content creation and
streaming video for the internet, as well as instructions for
digital signal processing (DSP) and communications
applications.
The AMD Sempron processor model 10 with 256K of L2 cache
features a seventh-generation microarchitecture with an
integrated, exclusive L2 cache, which supports the growing
processor and system bandwidth requirements of emerging
software, graphics, I/O, and memory technologies. The
high-speed execution core of the AMD Sempron processor
model 10 includes multiple x86 instruction decoders, a
dual-ported 128-Kbyte split level-one (L1) cache, an exclusive
256-Kbyte L2 cache, three independent integer pipelines, three
address calculation pipelines, and a superscalar, pipelined,
out-of-order, three-way floating-point engine. The floating-point
engine is capable of delivering top-of-the-class performance on
numerically complex applications.
The AMD Sempron processor model 10 with 256K of L2 cache
also includes QuantiSpeed™ architecture, a 333-MHz,
2.7-Gigabyte per second AMD Athlon™ system bus, and
3DNow! Professional technology. The AMD Athlon system bus
combines the latest technological advances, such as
point-to-point topology, source-synchronous packet-based
transfers, and low-voltage signaling to provide an extremely
powerful, scalable bus for an x86 processor.