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18 Power Management Chapter 4
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31994A —1 August 2004
4.3 Clock Control
The processor implements a Clock Control (CLK_Ctl) MSR
(address C001_001Bh) that determines the internal clock
divisor when the AMD Athlon system bus is disconnected.
Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,
Software, and Debug Developers Guide, order# 21656, for more
details on the CLK_Ctl register.