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14 AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide
GeodeLink™ Architecture
32430C
3.1 GeodeLink™ MSR Addressing
The GX processor’s MSRs are addressed from the source module to the port of the target module. The topology of the GX
processor must be understood to derive the address. An MSR address is parsed into two fields, the port address (18 bits)
and the index (14 bits). The port address is further parsed into six 3-bit channel address fields. Each 3-bit field represents,
from the perspective of the source module, the GLIU channels that are used to get to the destination module, starting from
the closest GLIU to the source (left most 3-bit field), to the farthest GLIU (right most 3-bit field). When the GLIU gets the
cycle, it reads the three MSBs of the address register, shifts those three bits of the 18 MSBs of the address register off, and
passes the transaction to the port indicated by the next three bits.
MSR addresses that are outside the module address spaces are invalid; meaning RDMSR/WRMSR instructions attempting
to use the address within the CPU core will cause a General Protection Fault. Unimplemented MSR accesses not in periph-
eral modules go to the bit bucket.
3.1.1 Addressing Example
GX Processor GeodeLink Modules/Addresses
Source: CPU Core -> Destination: GeodeLink Control Processor (GLCP)
2.3.0.0.0.0 -> 4C00xxxxh
CS5535 Companion Device GeodeLink Module/Addresses
Source: CPU Core -> Destination: SB_GLCP
2.4.2.7.0.0 -> 5170xxxxh
GLPCI acts like another GLIU
3.2 Descriptors
Descriptors are used to route memory or I/O resources through GLIUs to a GX processor module. Memory and I/O
addresses that do not have descriptors are subtractively decoded through the GLIUs and out to the PCI. It is important that
no descriptors overlap each other. The result is indeterminate.
3.2.1 Memory Descriptor Types
• Range - Covers a memory range in 4 KB granularity.
• Range Offset - Covers a memory range in 4 KB granularity with the destination address translated by an offset.
• Base Mask - Covers a memory range that is a power of 2 in size.
• Base Mask Offset - Covers a memory range that is a power of 2 in size with the destination address translated by an
offset.
• Swiss Cheese - Covers a 256 KB region split into 16 KB pieces to a module or the subtractive port.
3.2.2 I/O Descriptor Types
• Base Mask - Covers an I/O range that is a power of 2 in size.
• Swiss Cheese - Covers an 8-byte region split into 1-byte pieces to a module or the subtractive port.