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Functional Description
ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 2-6
ID031010 Non-Confidential
• Write fixed length bursts with HPROT[3] asserted to AXI fixed length bursts:
— The bridge sends an automatic OKAY response to all the AHB write data beats,
disregarding the B-channel AXI response. Therefore, if the network generates an
error response, it does not feed it back to the master.
— The bridge can support up to five outstanding write accesses because the RAW
hazard detection function supports up to four transactions. A fifth write is issued,
but the AHB write response is not issued until a slot is freed in the RAW hazard
monitor.
• Write fixed length bursts with HPROT[3] negated to AXI singles, and each AHB write
beat is acknowledged with the AXI buffered write response.
• Read INCR bursts with HPROT[3] asserted speculatively to AXI INCR4 bursts.
• Write INCR bursts with HPROT[3] asserted speculatively to AXI INCR4 bursts, and all
AHB write data beat receive an automatic OKAY response from the bridge irrespective
of the B-channel AXI response. Therefore, if the network generates an error response, it
does not feed it back to the master.
• Read INCR bursts with HPROT[3] negated to a series of AXI singles.
• Write INCR bursts with HPROT[3] negated to a series of AXI singles, and each AHB
write beat is acknowledged with the AXI buffered write response.
Combination 4
If you do not configure
INCR promotion and Early Write Response
and do not configure
allow
broken bursts
then the network converts all:
• read fixed length bursts to AXI fixed length bursts
• write fixed length bursts to AXI fixed length bursts, and only the last AHB write data beat
receives the AXI buffered response for the whole AHB transaction
• read INCR bursts to a series of AXI singles
• write INCR bursts to a series of AXI singles, and each AHB write beat is acknowledged
with the AXI buffered write response.
Note
If you select either the
INCR promotion and Early Write Response
or
allow broken bursts
configuration options, or both, then the following programmable function override bits also
exist and you configure a GPV port:
rd_incr_override
Converts all AHB read transactions to a series of AXI singles.
wr_incr_override
Converts all AHB write transactions to a series of AXI singles.
See Chapter 3 Programmers Model.
Error response
If the AHB master cancels a burst when it receives an ERROR response, the bridge stalls the
master until the network receives all the read data beats from the AXI domain. This is only
possible with read transfers because AXI writes receive a response at the end of the burst only.