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ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 3-8
ID031010 Non-Confidential
A configuration can contain a maximum of 64 security registers, that is, 1 < n < 64. Therefore,
if the configuration contains 64 master interfaces, then register security 63 is
0x10C
. These
registers are write-only because they are global accesses on the GPV.
Peripheral ID registers
If you configure any registers in the programmers view, peripheral ID registers are always
created. This provides a low gate count option for identification. Table 3-5 shows the peripheral
ID registers.
0x14
WO 1 - 16 -
security1
Slave 1 security setting. This consists of one bit for non- virtual slaves,
and up to 16 bits for virtual or APB master interfaces, and you can
configure the register bits as follows:
0 Secure.
1 Non-secure.
Note
For virtual or APB master interfaces with 16 security setting bits, each
bit position maps onto the region number. For example, the security1[5]
bit is the security setting for the address region for master interface node
number 1, region 5.
0x18
-
0x10C
WO 1 - 16 -
security<n>
Slave n security setting. It contain one bit for non-virtual slaves, and up
to 16 bits for APB master interfaces.
0x110
-
0xFFF
RO - - - Reserved.
Table 3-4 Address region control registers (continued)
Address
offset
Type Width
Reset
value
Name Description
Table 3-5 Peripheral ID registers
Address
offset
Type Width
Reset
value
Name Description
0x0
-
0xFCC
RO - - - Reserved
0xFD0
RO 8
0x04
Peripheral ID4 4KB count, JEP106 continuation code
0xFD4
RO 8
0x00
Peripheral ID5 Reserved
0xFD8
RO 8
0x00
Peripheral ID6 Reserved
0xFDC
RO 8
0x00
Peripheral ID7 Reserved
0xFE0
RO 8
0x01
Peripheral ID0 Part Number [7:0]
0xFE4
RO 8
0xB3
Peripheral ID1 JEP106[3:0], part number [11:8]
0xFE8
RO 8
0x4B
Peripheral ID2 Revision, JEP106 code flag, JEP106[6:4]
0xFEC
RO 8
0x00
Peripheral ID3 You can set this using the AMBA Designer Graphical User Interface
(GUI)
0xFF0
RO 8
0x0D
Component ID0 Preamble