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4-26 Chapter 4: BIOS setup
4.4.5 Chipset
The Chipset menu allows you to change the advanced chipset settings. Select an
item then press <Enter> to display the sub-menu.
Advanced Chipset Settings
Congure DRAM Timing by SPD [Enabled]
DRAM ECC Mode [Disabled]
Hyper Path 3 [Auto]
DRAM Throttling Threshold [Auto]
Boot Graphic Adapter Priority [PCI Express/PCI]
PEG Buffer Length [Auto]
Link Latency [Auto]
PEG Root Control [Auto]
PEG Link Mode [Auto]
Slot Power [Auto]
Enable or Disable
Congure DRAM
Timing by SPD.
Congure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according to the
DRAM SPD (Serial Presence Detect). When disabled, you can manually set the
DRAM timing parameters through the DRAM sub-items. The following sub-items
appear when this item is Disabled. Conguration options: [Disabled] [Enabled]
DRAM CAS# Latency [5 Clocks]
Controls the latency between the SDRAM read command and the time the
data actually becomes available. Conguration options: [6 Clocks] [5 Clocks]
[4 Clocks] [3 Clocks]
DRAM RAS# Precharge [4 Clocks]
Controls the idle clocks after issuing a precharge command to the DDR SDRAM.
Conguration options: [2 Clocks] ~ [6 Clocks]
DRAM RAS# to CAS# Delay [4 Clocks]
Controls the latency between the DDR SDRAM active command and the
read/write command. Conguration options: [2 Clocks] ~ [6 Clocks]
DRAM RAS# Activate to Precharge Delay [15 Clocks]
Conguration options: [4 Clocks] ~ [18 Clocks]
DRAM Write Recovery Time [4 Clocks]
Conguration options: [2 Clocks] ~ [6 Clocks]