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4173ES–USB–09/07
AT89C5132
6.3.3.2 Timings
Table 13. SPI Interface Master AC Timing
V
DD
= 2.7 to 3.3V, T
A
= -40° to +85°C
Notes: 1. Value of this parameter depends on software.
2. Test conditions: capacitive load on all pins = 100 pF
Symbol Parameter Min Max Unit
Slave Mode
T
CHCH
Clock Period 8 T
OSC
T
CHCX
Clock High Time 3.2 T
OSC
T
CLCX
Clock Low Time 3.2 T
OSC
T
SLCH
, T
SLCL
SS Low to Clock edge 200 ns
T
IVCL
, T
IVCH
Input Data Valid to Clock Edge 100 ns
T
CLIX
, T
CHIX
Input Data Hold after Clock Edge 100 ns
T
CLOV,
T
CHOV
Output Data Valid after Clock Edge 100 ns
T
CLOX
, T
CHOX
Output Data Hold Time after Clock Edge 0 ns
T
CLSH
, T
CHSH
SS High after Clock Edge 0 ns
T
IVCL
, T
IVCH
Input Data Valid to Clock Edge 100 ns
T
CLIX
, T
CHIX
Input Data Hold after Clock Edge 100 ns
T
SLOV
SS Low to Output Data Valid 130 ns
T
SHOX
Output Data Hold after SS High 130 ns
T
SHSL
SS High to SS Low
(1)
T
ILIH
Input Rise Time 2 μs
T
IHIL
Input Fall Time 2 μs
T
OLOH
Output Rise Time 100 ns
T
OHOL
Output Fall Time 100 ns
Master Mode
T
CHCH
Clock Period 4 T
OSC
T
CHCX
Clock High Time 1.6 T
OSC
T
CLCX
Clock Low Time 1.6 T
OSC
T
IVCL
, T
IVCH
Input Data Valid to Clock Edge 50 ns
T
CLIX
, T
CHIX
Input Data Hold after Clock Edge 50 ns
T
CLOV,
T
CHOV
Output Data Valid after Clock Edge 65 ns
T
CLOX
, T
CHOX
Output Data Hold Time after Clock Edge 0 ns
T
ILIH
Input Data Rise Time 2 μs
T
IHIL
Input Data Fall Time 2 μs
T
OLOH
Output Data Rise Time 50 ns
T
OHOL
Output Data Fall Time 50 ns