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A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
SCL
POWERON
GGE[7:0]GGE[7:0]
CS0n CS0n
A0
ROMWEn
DVS
ECO-MODE
BHENn
RESET
A[19:1]
DEN
GVSGVS
DCKEXT
GRE[7:0]GRE[7:0]
SDA
DGE[7:0]
DBE[7:0]
RESETZ
DCLK
GCOASTGCOAST
GFBKGFBK
LAMPLITZ
FAN_P
GBE[7:0]GBE[7:0]
GCLKGCLK
GBLKSPLGBLKSPL
CS1nCS1n
ROMOEn
D[0:15]
GHSGHS
VPPEN
DHS
POWERON
KEYSTONE
DRE[7:0]
MCKEXT
SDA
IRRCVR
IRRCVR
GAIN_C GAIN_C
BAIN_C BAIN_C
CONTROL
HSYNC HSYNC
RAIN_C RAIN_C
TXDTXD
VSYNC_C VSYNC_C
RXD RXD
VHSVHSCVBSCVBS
GAIN_V
VVSVVS
VY[7:0]VY[7:0]
BAIN_V
CHROMACHROMA
SDA
LUMALUMA
VUV[7:0]VUV[7:0]
VCLKVCLK
VFIELDVFIELD
VPENVPEN
RAIN_V
AVDD
SCL
RESETn
SCL
SDA
SCL
D[0:7]
D[0:7]
3.3V
VDD
SCL
SDA
GND
POWERON
DEN
RESETZ
LAMPLITZ
DGE[7:0]
DHS
DRE[7:0]
DCLK
DVS
DBE[7:0]
ECO-MODE
FAN_P
VDD
3.3V
VDD
VDD
3.3V
VDD
3.3V
3.3V
VDD
3.3V
VDD
V33
VDD
V33
Title
Size Document Number Rev.
Date: Sheet
of
Project Code
Reviewed By Approved By
Prepared By
Model Name
PCB P/N
PCB Rev.
Benq Corporation
OEM/ODM Model Name
48.J8601.S04
MAIN BOARD
220
DAVID HN LIN KELVIN LIAO
99.J8677.B12-C3-304-004S04
ANGEL HU
<Size>
PB610099.J8677.001
1
Tuesday, October 07, 2003
<OEM/ODM>
Note: To DDP1000 input port
Note: Lamp on/off detect signal.
Note: PW164B RS232 I/O port connect with
PC ( for control ) and Ballast ( for lamp
stasus )
Regect RC1 and RC2 before connect DX660 main board with
INTERFACE board.
PAGE_10
015_PW166
VCLK
VFIELD
VVS
VHS
VPEN
VY[7:0]
GGE[7:0]
GRE[7:0]
GVS
GBLKSPL
GHS
GFBK
GCLK
GBE[7:0]
GCOAST
TDO
TXD
ROMWEn
TCK
RXD
MCKEXT
ROMOEn
IRRCVR
TMS
A[19:1]
DCKEXT
RESET
D[0:15]
SDA
DVS
DHS
DRE[7:0]
DCLK
DGE[7:0]
DBE[7:0]
A0
BHENn
DEN
VUV[7:0] POWERON
RESETZ
DRO[7:0]
DGO[7:0]
DBO[7:0]
SCL
VPPEN
AUDIO_MUT
3.3V
CS0n
LAMPLITZ
GND
ECO-MODE
KEYSTONE
AUDIO_VOL
CS1n
FAN_P
VDD
D[0:7]
CONTROL
key8
DECODE
012_DECODE
VDD
VUV[7:0]
SCL
SDA
V33
VY[7:0]
VHS
VVS
VPEN
CVBS
VCLK
VFILD
LLC1
LLC2
LUMA
CHROMA
GAIN_V
RAIN_V
BAIN_V
AVDD
GND
PAGE_12
017_KEY
D[0:7]
CS0nVDD
3.3V
GND
CS1n
RESETn
IRRCVR
key8
PAGE_11
016_MISC
POWERON
DCKEXT
MCKEXT
VDD
3.3V
GND
KEYSTONE
SDA
SCL
PAGE_8
013_AFE
SCL
SDA
GBLKSPL
GCOAST
HSYNC
GBE[7:0]
GGE[7:0]
GRE[7:0]
GFBK
GHS
GVS
GCLK
VDD
GND
RAIN_C
GAIN_C
BAIN_C
VSYNC_C
RAIN_V
GAIN_V
BAIN_V
AVDD
V33
INPUT
011_INPUT
RXD
TXD
HSYNC
BAIN_C
RAIN_C
GAIN_C
VSYNC_C
CONTROL
VDD
3.3V
GND
CVBS
LUMA
CHROMA
PAGE_9
014_MEMORY&KEYSTONE
VPPEN
A[19:1]
D[0:15]
3.3V
GND
ROMWEn
ROMOEn
SCL
SDA
A0
BHENn
RESET
RESETn
VDD