Filter
Top Products
SDM-SW8A Switch Closure Input Module
7. Datalogger Program Details
7.1 Datalogger Scan Rate
The Module samples channel state every 2 ms and accumulates the information
for duty cycle and counts. Each channel has one 16 bit accumulator for duty
cycle and one for counts. The accumulators are reset when the datalogger
requests information from the SW8A and when the count exceeds 65535. The
datalogger scan rate must be frequent enough to avoid SW8A accumulator
overflow.
Each Duty Cycle accumulator resets every 131 seconds (2 ms * 65536) or
roughly 2 minutes. If Duty Cycle is requested, the datalogger scan rate must
be less than 131 seconds.
The rate at which Count accumulators are reset is input frequency dependent.
For example, at a maximum input frequency of 100 Hz, the datalogger must
sample the SW8A at least every 655 seconds (approximately 10 minutes) or
the accumulator for that channel resets and starts over again.
7.2 First Scan
From the time power is applied, the SW8A samples the state of all channels
every 2 ms. The first time the datalogger executes Instruction 102 and requests
information, the results represent the time period since the SW8A was powered
up, not the datalogger scan interval. This problem may be avoided by ignoring
the data from the first scan after the datalogger is compiled. The example
program (see Appendix) includes a routine which discards first scan data.
7.3 Watchdog Reset
Any microprocessor may occasionally fail due to input transients or
intermittent component failure (e.g., a bombed condition). The SW8A has a
"watchdog" counter which resets the processor under such conditions. When
functioning normally, the processor resets the watchdog counter. To transfer
data between the datalogger and the SW8A, the datalogger drives the clock
line, Control Port 2, high and low (refer to Theory of Operation, Section 9).
The watchdog counts clock line transitions, and if the count exceeds 64, the
watchdog resets the SW8A processor. Requesting State produces 16 clock
transitions. Duty Cycle and Count each produce 24 + 16 clock transitions per
channel.
The length of time that the SW8A stays bombed before a watchdog reset
occurs is a function of the datalogger scan rate and the amount of information
requested from the Module. For example, if the datalogger scan rate is 10
minutes, and 2 channels of counts are requested, the SW8A may stay bombed
for 20 minutes. To avoid this undesirable time delay before resetting, a
trapping routine may be programmed into the datalogger to detect a bombed
condition and immediately force a watchdog reset.
The trapping routine keys on the fact that -99999 is stored in input locations
when the Module is bombed (-99999 is also stored if the Module is incorrectly
addressed or wired wrong). When -99999 is detected, the routine immediately
9