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Cisco 12404 Internet Router Installation and Configuration Guide
OL-11636-01
Appendix A Technical Specifications
Product Architecture
MBus Module Port Pin Assignments
Twenty general purpose pins and four analog input pins on the MBus module are
used for this design.
CSF Functionality
The CSF circuity provides synchronized speed interconnections for the line cards
and the RP (Figure A-5). The CSF circuitry consists of clock and scheduler, and
switch fabric functionality; is contained on one card, housed in the bottom slot in
the chassis. The CSF card has a switching capacity of 40 Gbps.
Figure A-5 CSF Card Slot
Clock and Scheduler Functionality
The CSF card generates and distributes system-wide clock and cell time
synchronization signaling. System clock generation is delivered to the system via
the backplane and local clock functions are derived from the system clock.
System Clock
The system clock synchronizes data transfers between line cards or between the
RP and a line card through the CSF. The system clock signal is sent to all line
cards and the RP.
66293
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