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Schematic Diagrams
Clock Generator B - 19
B.Schematic Diagrams
Clock Generator
CLK_PCIE_MINI_3G
Z1740
C488 *10P_50V_04
C534
10U_10V_08
Z1726
R279 33_04
BSEL0
SELLCD_27#=0
Z1712
R268 10K_04
C502
0.1U_10V_X7R_04
1
MCH_CLKREQ#
(P E RE Q2#)
CLK_BSEL1 [2,4]
REF_14.318M
CLK_PC IE_NEW_CAR D#
R284 2.2K_04
DOT96
3.3VM_CLK
C499 *10P_50V_04
3.3VM_CLK
X3
14.318MHz
1 2
CLK_DREF
C LK_CP U_BCLK
CLK_PC IE_3GPLL#
C507 *10P_50V_04
PCIEX9
CLK_PCIE_3GPLL
R293 *10mil_short
CLK_ICH 48
Red words must be controlled by BIOS
CLK_PWRGD[15]
Z1733
CLK_PC IE_MINI#
C466 *10P_50V_04
R272 33_04
27FIX/SS
CLK_DREF#
RN24
4P2RX33_04
1 4
2 3
C468
0.1U_10V_X7R_04
Z1735
Z1704
RN21
4P2RX33_04
14
23
1
SELLCD_27#
PCLK_ICH33[14]
MCH_ CL KREQ# [5 ]
667 MHz166 MHz
CLK_DREF # [5]
L39
HCB1608KF-121T25
WLAN_C LKREQ#
(P E RE Q3#)
PM_STPPC I#[15]
CLK_ICH 14
CLK_SATA
FSLA
Z1736
R295 300_1%_04
PCIEX9
CLK_PCIE_MINI_3G #
R271 33_04
U22
ICS9LPR363EGLF
5
11
56
62
49
51
35
48
52
2
6
8
55 16
61
12
42
34
58
57
45
36
33
60
3
4
28
50
54
9
64
13 21
37
53
32
30
31
27
26
24
25
23
22
19
20
18
17
14
15
10
47
7
1
29
46
39
38
41
40
44
43
59
63
PCICLK3/*SELPCIEX0_LCD#
VDD48
VDDREF
CPU_STOP#
CPUT_L1F
CPUC_L0
PCIeC_L5
CPU C_L1F
CPUT_L0
GND
GND
PCICLK_F4/ITP_EN
SDATA FSLB/TEST_MODE
REF1/FSLC/TEST_SEL
FSLA/USB_48MHz
VDDPCIEX
*PWRS AVE#
X1
X2
VDDA
PCIeT_L5
*PER EQ4#
REF0_14.318M
PCICLK1
PCICLK2
VDDPCIEX
VDDCPU
SCLK
*SELLCD_27#/PCICLK_F5
**PCIC LK0/REQ_SEL
GND VDDPCIEX
GND
GND
*PER EQ3#
PCIeT_L4
PCIeC_L4
SATACLKC_L
SATACLKT_L
PCIeT_L3
PCIeC_L3
PCIeC_L2
PCIeT_L2
PCIeT_L1
PCIeC_L1
27SS/LCD_SSCGC/PCIeC_L0
27FIX/LCD_SSCGT/PCIeT_L0
PCIeT_L9/DOTT_96MHzL
PCIeC_L9/DOTC_96MHzL
VTT_PW R_GD /PD#
VREF
VDDPCI
VDDPCI
GND
GNDA
PCIeT_L6
PCIeC_L6
PCIeT_L7/PEREQ1#
PCIeC _L7/PEREQ2#
PCIeT_L8/CPUITPT_L2
PCIeC_L8/CPUITPC_L2
GND
PCI/PCIEX_STOP#
CLK_PCIE_MINI [20]
C492 *10P_50V_04
RN28
4P2RX33_04
14
23
RN31
4P2RX33_04
1 4
2 3
C471
27P_50V_04
CK505
1066 MHz
PCIECLK 4 (JM385)
LCD(96MHz)
C532
0.1U_10V_X7R_04
C498 *10P_50V_04
CLK_PC IE_ICH
CLK_DREFSS
C474 *10P_50V_04
BSEL2
CLK_MC H_BCLK
PCLK_TPM
Z1723
PCLK_ICH33
C509 *10P_50V_04
CLK_ICH 48
C449 *10P_50V_04
CLK_SATA
PCLK_TPM
Z1728
Layout note:
LAN_CLKREQ #
(P E RE Q4#)
FSLC
ICH_SMBDAT0[10,11,15]
CLK_PC IE_MINI_3G
XTAL_IN
PCIECLK 2 (MINI)
3.3VS
CLK_PCIE_MIN I_3G# [19]
CLK_CPU _B CLK
CLK_CPU_BC LK# [2]
CLK_DREFSS#
RN26
4P2RX33_04
14
23
C484 *10P_50V_04
C494 *10P_50V_04
PCIEX0
PCLK_ICH33
C501 *10P_50V_04
CLK_BSEL2[2,4]
C491
0.1U_10V_X7R_04
PCIECLK 8 (ICH)
BSEL1
DOT96
3.3VM_CLK
PCLK_TP M[19]
SATACLK
CLK_DREF SS [5]
CLK_PCIE_GLAN [23]
CLK_PCIE_MINI
CLK_PC IE_MINI_3G#
RN30
4P2RX33_04
1 4
2 3
C536 *10P_50V_04
C542 *10P_50V_04
Z1713
C490 *10P_50V_04
SELPCIEX0_LCD#/
CLK_PCIE_GLAN #
R267 33_04
CLK_ICH48[15]
30mils
CLK_PCIE_MIN I_3G [19]
Z1725
0
Pin14/15
PCIECLK 3 (MI NI_ 3G )
C528 *10P_50V_04
C497 *10P_50V_04
0
CLK_SATA#
R296
1K_1%_04
SELLCD_27#=1
LAN _CLKREQ# [23]
CLK_DREFSS
CLK_SATA#
Z1731
CLOCK GENERATOR
Z1730
R269 10K_04
SELLCD_27#=1
R307 475_1%_04
PCIECLK 1 (3GP LL)
CLK_CPU_BC LK [2]
CLK_MC H_BCLK#
CLK_PCIE_GLAN# [23]
CLK_PCIE_ICH [14]
Z1741
SELPCIEX0_LCD#/
CLK_PCIE_JM380# [22]
C481 *10P_50V_04
Insatlled: Differential clock
level is higher
PCIECLK 6 (NEW CARD)
CLK_PCIE_NEW_C ARD
PCLK_KBC
C541 *10P_50V_04
C512 *10P_50V_04
CLK_DREFSS#
Z1732
Z1729
C537 *10P_50V_04
R253 *10K_04
C475 *10P_50V_04
CLK_PCIE_NEW_C ARD#
Frequency
PCIEX0
CLK_PCIE_MINI#
Layout note:
CLK_PCIE_3GPLL [5]
CLK_PCIE_JM380
Z1742
3.3VS
PCLK_KBC
CLK_MCH_BC LK
RN32
4P2RX33_04
1 4
2 3
0
Z1724
PCLK_KBC[26]
C450 *10P_50V_04
Z1710
CLK_PC IE_MINI
PCI3 = 1 (high)
Z1711
CLK_PC IE_3GPLL
PLACE CRYSTAL WITHIN
500 MILS OF
ICS9LPR363EGLF
200 MHz
CLK_CPU _B CLK#
C511
1U_6.3V_04
SATA_CLKREQ#
(P E RE Q1#)
800 MHz
Z1718
CLK_PC IE_GLAN
C533 *10P_50V_04
FSLA
PM_STPCPU#[15]
CLK_PCIE_ICH# [14]
CLK_DREF SS# [5]
CLK_MCH_BC LK#
SELPCIEX0_LCD#
PCI3 = 0 (low)
CLK_PCIE_IC H
Z1719
CLK_PCIE_JM380 [22]
CLK_PCIE_3GPLL#
CLK_PCIE_GLAN
Z1715
Z1738
Z1703
C LK_CP U_BCLK#
Host Clock
Z1722
PCIECLK 5 (GLAN)
3.3VS
CLK_MCH_BCLK# [4]
C472
27P_50V_04
0
WLAN_CLKREQ# [19,20]
Z1714
C478
*10U_10V_08
RN22
4P2RX33_04
1 4
2 3
Default
Place termination close
to ICS9LPR363DGLF
CLK_DR EF#
C519 *10P_50V_04
Z1727
C467
1U_6.3V_04
C487 *10P_50V_04
1
CLK_MCH _BCLK [4]
CLK_PC IE_ICH#
CLK_P CIE_NEW_CA RD# [20]
C482
0.1U_10V_X7R_04
0
CLK_ICH 14
FSLC
C543 *10P_50V_04
R282 *100K_04
Pin5
REQ _SEL
C505 *10P_50V_04
Layout note:
3.3VS[5,8..16,19. .27,31]
CLK_PCIE_JM380#
CLK_PC IE_NEW_CAR D
CLK_ICH14[15]
266 MHz
SATA _CLKREQ# [15]
ICH_SMBCLK0[10,11,15]
XTAL_OU T
C480
0.1U_10V_X7R_04
RN29
4P2RX33_04
14
23
20mils
Pin17/18
CLK_BSEL0[2,4]
CLK_DREF [5]
C544 *10P_50V_04
FSLB
CLK_SATA# [13]
CLK_PC IE_JM380
Pin9
CLK_SATA [13]
CLK_PCIE_NEW_CARD [20]
RN23
4P2RX33_04
14
23
C535
10U_10V_08
C500
1U_6.3V_04
R306 475_1%_04
CLK_PCIE_IC H#
CLK_PC IE_JM380#
ITP_E N
0
CLK_PCIE_3GPLL# [5]
40mils
CLK_PCIE_MIN I# [20]
FSLB
R265 10K_04
R266 *33_04
RN25
4P2RX33_04
14
23
SELLCD_27#=0
CLK_DR EF
CLK_PC IE_GLAN#
RN27
4P2RX33_04
14
23
Sheet 18 of 40
Clock Generator