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Schematic Diagrams
B - 28 3G, Powergood
B.Schematic Diagrams
3G, Powergood
20 mil
P CIE_RXN 3_3G23
3.3VS
UIM_RST
3G_EN 34
GND
Z2701
3.3V S2 ,3,6,7,10, 12,13,14,15,22,23,24,25,26,28,29,30,31,32,33,34,35,39,41,43
C735
*22P_50V_0 4
GND
1.5V S
R448 *0_04
CLK_PCIE_MINI_3G#2
GND
3.3VS
GND
Z 2704
GND
USB_PN2 23
1.5VS
UIM_CLK
C740
* 22P_50V_04
PC IE _TXP3_3G23
PCIE_RXP3_3G23
R477 0_04
GND
PCIE_ WAKE#24,26, 31
UIM_PWR
PCIE_TXN3_3G23
UIM_VPP
3.3VS
1.5VS
1.5VS4 ,10,22,23,25,26,32 ,35
CLK_PC IE_MIN I_3G2
WLAN_CLKREQ#2,26
UIM_VPP
UIM_DATA
GND
C737
* 22P_50V _04
GND
C694
.1U_16V_04
UIM_PWR
UIM_CLK
3G_DET#34
GND
C695
10U_10V _08
KEY
J_3G1
88908-5204
3
5
7
9
11
13
1
15
23
25
21
27
31
33
29
17
19
20
37
39
41
43
45
47
49
51
44
42
18
16
14
2
12
10
8
6
4
22
24
26
28
30
32
34
36
38
40
46
48
50
52
35
COEX1
COEX2
CLKREQ#
GND0
REFCLK-
REFCLK+
WAKE#
GND1
PETn 0
PETp 0
GND2
GND3
PER n0
PER p0
GND4
Reserve d0
Reserve d1
W_DISABLE#
GND12
3.3V AU X_3
3.3V AU X_4
GND13
Reserve d2
Reserve d3
Reserve d4
Reserve d5
LED _WLAN #
LED _WWAN#
GND6
UIM_VPP
UIM_RESET
3.3V AU X_0
UIM_CLK
UIM_DATA
UIM_PWR
1.5V_0
GND5
PERSET#
3.3V AU X_1
GND7
1.5V_1
SMB_ CL K
SMB_DATA
GND8
USB_D-
USB_D+
GND9
LE D_WPAN#
1.5V_2
GND10
3.3V AU X_2
GND11
R507 *4.7K_04
C66
.1U _16V_04
C199
.1U_16V_04
3.3V S
USB_PP223
UIM_RST
C213
.1U_16V_04
R503 0_04
C179 .1U_16V_04
+
C697 220U_4 V_D2
Port 2
+
C696
220U_4V _D2
GND
Z27 03
BUF_ P L T_R ST# 23 , 26 ,2 9,3 1, 3 4
SIM CONN
(TOP VIEW)
LOCK
OPEN
J_SI M1
SIMLOCK 1770661-1
C7
C6
C5C1
C2
C3
UIM_DATA
UIM_VPP
UIM_GNDUIM_PWR
UIM_RST
UIM_CLK
C742
* 22P_50V_04
3G
UIM_DATA
5VS 14,22, 25,28,30,32,33,35,43
GND
Z2702
GND
3.3V 3, 14, 15, 22,23,24,25,26,28,30,31,35,37, 38
3.3V S
GND
GND
R508 0_04
GND
Sheet 27 of 51
3G, Powergood