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Appendix
COM-2(PC)F 57
Baud Rate Selection
The COM-2(PC)F board has one programmable baud rate generator
for each of the two ACEs. The ACEs use a 1.8432MHz crystal
oscillator as clock input. The baud rate generator takes the
1.8432MHz clock and divides it by a divisor from 1 to (2
16
- 1).
The output frequency of the baud rate generator equals 16 times the
baud rate.
Based on the originating clock frequency, the baud rate is derived
as:
Divisor = clock frequency/(baud rate x 16)
Two eight-bit divisor registers on the ACEs store the divisor in a
16-bit binary format. These divisors must be loaded during
initialization into Divider registers (see Table 6.6.). Table 6.7.
provides frequently used baud rates and their divisors. The
percent error is the difference between actual and desired value.
Table 6.7. Baud Rate and Divisors
Desired Baud Rate Divisor Percent Error
50 2304 ---
75 1536 ---
110 1047 0.026
134.5 857 0.058
150 768 ---
300 384 ---
600 192 ---
1200 96 ---
1800 64 ---
2000 58 0.680
2400 48 ---
3600 32 ---
4800 24 ---
7200 16 ---
9600 12 ---
19200 6 ---
38400 3 ---
57600 2 ---
115200 1 ---