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Appendix
COM-2(PC)F 63
Table 6.9. NS16550's Register
(Short from National Semiconductor's data book)
< 2 / 2 >
Register
4 5 6 7 0 DLAB = 1 1 DLAB =1
Bit MODEM Line MODEM Scratch Divisor Divisor
No. Control Status Status Register Latch Latch
Register Register Register (LS) (MS)
MCR LSR MSR SCR DLL DLM
0 Data Data Delta Bit 0 Bit 0 Bit 8
Terminal Ready Clear
Ready (DR) to Send
(DTR) (DCTS)
1 Request Overrun Delta Bit 1 Bit 1 Bit 9
to Send Error Data
(RTS) (OE) Set Ready
(DDSR)
2 Out 1 Parity Trailing Bit 2 Bit 2 Bit 10
Error Edge Ring
(PE) Indicator
(TERI)
3 Out 2 Framing Delta Bit 3 Bit 3 Bit 11
Error Data
(FE) Carrier
Detect
(DDCD)
4 Loop Break Clear Bit 4 Bit 4 Bit 12
Interrupt to Send
(BI) (CTS)
5 0 Transmitter Data Bit 5 Bit 5 Bit 13
Holding Set
Register Ready
(THRE) (DSR)
6 0 Transmitter Ring Bit 6 Bit 6 Bit 14
Empty Indicator
(TEMT) (RI)
7 0 Error in Data Bit 7 Bit 7 Bit 15
RCVR Carrier
FIFO Detect
(DCD)