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3. Hardware Installations
SPI-8451-LLVA, SPI-8452-LLVA, SPI-8451-LVA
25
IDE RAID Connector: CN14, CN8
(SPI-8451-LLVA only)
The CPU board SPI-8451-LLVA using the chipset of Promise PDC20265R for IDE RAID port that with
the bus-mastering design takes full advantage of multi-tasking, multi-threading operating systems and
greatly improves performance.
Provides scatter/gather DMA mechanism that complies with Revision 1.0 of the programming interface
for Bus Master IDE Controller.
Scatter/Gather mechanism supports both DMA and PIO IDE drives and ATAPI devices. Allows
byte-boundary memory region during Bus Master DMA transfers which benefits operating systems or
applications, which has odd byte boundary memory transfers.
Dual independent data paths with read ahead and write posting for each channel supported for dual IDE
channels to balanced bus loading and optimal performance.
Table 3.10. IDE RAID Connector
Pin No.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Function
RESET
D7
D6
D5
D4
D3
D2
D1
D0
GND
DREQ
IOW
IOR
IORDY
DACK
IRQ
A1
A0
CS0
HD ACT
Pin No.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Function
GND
D8
D9
D10
D11
D12
D13
D14
D15
N.C.
GND
GND
GND
ALE
GND
N.C.
P66DET
A2
CS1
GND
CN14/CN8
1
2
39
40