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CY62128E
Document #: 38-05485 Rev. *F Page 5 of 12
Switching Characteristics (Over the Operating Range)
[12]
Parameter Description
45 ns (Ind’l/Auto-A) 55 ns (Auto-E)
Unit
Min Max Min Max
Read Cycle
t
RC
Read Cycle Time 45 55 ns
t
AA
Address to Data Valid 45 55 ns
t
OHA
Data Hold from Address Change 10 10 ns
t
ACE
CE
1
LOW and CE
2
HIGH to Data Valid 45
55
ns
t
DOE
OE LOW to Data Valid 22
25
ns
t
LZOE
OE LOW to Low-Z
[13]
5
5
ns
t
HZOE
OE HIGH to High-Z
[13, 14]
18
20
ns
t
LZCE
CE
1
LOW and CE
2
HIGH to Low-Z
[13]
10
10
ns
t
HZCE
CE
1
HIGH or CE
2
LOW to High-Z
[13, 14]
18
20
ns
t
PU
CE
1
LOW and CE
2
HIGH to Power Up 0
0
ns
t
PD
CE
1
HIGH or CE
2
LOW to Power Down 45
55
ns
Write Cycle
[15]
t
WC
Write Cycle Time 45 55 ns
t
SCE
CE
1
LOW and CE
2
HIGH to Write End 35
40
ns
t
AW
Address Setup to Write End 35 40 ns
t
HA
Address Hold from Write End 0
0
ns
t
SA
Address Setup to Write Start 0 0 ns
t
PWE
WE Pulse Width 35
40
ns
t
SD
Data Setup to Write End 25 25 ns
t
HD
Data Hold from Write End 0 0 ns
t
HZWE
WE LOW to High-Z
[13, 14]
18
20
ns
t
LZWE
WE HIGH to Low-Z
[13]
10
10
ns
Notes
12.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns (1V/ns) or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3V, and output loading of the specified I
OL
/I
OH
as shown in the “” on page 4.
13.At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
14.t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
15.The internal Write time of the memory is defined by the overlap of WE
, CE
= V
IL
. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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