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CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Document #: 38-06070 Rev. *H Page 15 of 32
t
OE
Output Enable to Data Valid 4.0 4.4 4.7 5.0 ns
t
OLZ
[20, 21]
OE to Low Z 0 0 0 0 ns
t
OHZ
[20, 21]
OE to High Z 04.004.404.705.0ns
t
CD2
Clock to Data Valid 4.0 4.4 4.7 5.0 ns
t
CA2
Clock to Counter Address Valid 4.0 4.4 NA NA ns
t
CM2
Clock to Mask Register Readback Valid 4.0 4.4 NA NA ns
t
DC
Data Output Hold After Clock HIGH 1.0 1.0 1.0 1.0 ns
t
CKHZ
[20, 21]
Clock HIGH to Output High Z 0 4.0 0 4.4 0 4.7 0 5.0 ns
t
CKLZ
[20, 21]
Clock HIGH to Output Low Z 1.0 4.0 1.0 4.4 1.0 4.7 1.0 5.0 ns
t
SINT
Clock to INT Set Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns
t
RINT
Clock to INT Reset Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns
t
SCINT
Clock to CNTINT Set Time 0.5 5.0 0.5 5.7 NA NA NA NA ns
t
RCINT
Clock to CNTINT Reset time 0.5 5.0 0.5 5.7 NA NA NA NA ns
Port to Port Delays
t
CCS
Clock to Clock Skew 5.2 6.0 6.0 8.0 ns
Master Reset Timing
t
RS
Master Reset Pulse Width 7.0 7.5 7.5 10.0 ns
t
RSS
Master Reset Setup Time 6.0 6.0 6.0 8.5 ns
t
RSR
Master Reset Recovery Time 6.0 7.5 7.5 10.0 ns
t
RSF
Master Reset to Outputs Inactive 10.0 10.0 10.0 10.0 ns
t
RSCNTINT
Master Reset to Counter Interrupt Flag
Reset Time
10.0 10.0 NA NA ns
Switching Characteristics
Over the Operating Range (continued)
Parameter Description
-167 -133 -100
Unit
CY7C0850AV
CY7C0851AV
CY7C0852AV
CY7C0850AV
CY7C0851AV
CY7C0852AV
CY7C0853AV CY7C0853AV
Min Max Min Max Min Max Min Max
Notes
20.This parameter is guaranteed by design, but it is not production tested.
21.Test conditions used are Load 2.
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