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CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Document #: 38-05543 Rev. *F Page 24 of 34
Figure 11. Write Cycle Timing
[26, 27]
Switching Waveforms (continued)
t
CYC
t
CL
CLK
ADSP
t
ADH
t
ADS
ADDRESS
t
CH
OE
ADSC
CE
t
AH
t
AS
A1
t
CEH
t
CES
BWE,
BW
X
ata Out (Q)
High-Z
ADV
BURST READ BURST WRITE
D(A2) D(A2 + 1) D(A2 + 1)
D(A1)
D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)
A2 A3
Data In (D)
Extended BURST WRITE
D(A2 + 2)
Single WRITE
t
ADH
t
ADS
t
ADH
t
ADS
t
OEHZ
t
ADVH
t
ADVS
t
WEH
t
WES
t
DH
t
DS
GW
t
WEH
t
WES
Byte write signals are
ignored for first cycle when
ADSP initiates burst
ADSC extends burst
ADV suspends burst
DON’T CARE
UNDEFINED
Note
27.
Full width write can be initiated by either GW
LOW; or by GW HIGH, BWE LOW and BW
X
LOW
.
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