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CY7C604XX
Document Number: 001-12395 Rev *H Page 12 of 30
Table 5. Register Map Bank 0 Table: User Space
Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW 40 80 C0
PRT0IE 01 RW 41 81 C1
02 42 82 C2
03 43 83 C3
PRT1DR 04 RW 44 84 C4
PRT1IE 05 RW 45 85 C5
06 46 86 C6
07 47 87 C7
PRT2DR 08 RW 48 88 I2C_XCFG C8 RW
PRT2IE 09 RW 49 89 I2C_XSTAT C9 R
0A 4A 8A I2C_ADDR CA RW
0B 4B 8B I2C_BP CB R
PRT3DR 0C RW 4C 8C I2C_CP CC R
PRT3IE 0D RW 4D 8D CPU_BP CD RW
0E 4E 8E CPU_CP CE R
0F 4F 8F I2C_BUF CF RW
PRT4DR 10 RW 50 90 CUR_PP D0 RW
PRT4IE 11 RW 51 91 STK_PP D1 RW
12 52 92 D2
13 53 93 IDX_PP D3 RW
14 54 94 MVR_PP D4 RW
15 55 95 MVW_PP D5 RW
16 56 96 I2C_CFG D6 RW
17 57 97 I2C_SCR D7 #
18 58 98 I2C_DR D8 RW
19 59 99 D9
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C INT_CLR2 DC RW
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK2 DE RW
1F 5F 9F INT_MSK1 DF RW
20 60 A0 INT_MSK0 E0 RW
21 61 A1 INT_SW_EN E1 RW
22 62 A2 INT_VC E2 RC
23 63 A3 RES_WDT E3 W
24 64 A4 INT_MSK3 E4 RW
25 65 A5 E5
26 66 A6 E6
27 67 A7 E7
28 68 A8 E8
SPI_TXR 29 W 69 A9 E9
SPI_RXR 2A R 6A AA EA
SPI_CR 2B # 6B AB EB
2C 6C AC EC
2D 6D AD ED
2E 6E AE EE
2F 6F AF EF
30 70 PT0_CFG B0 RW F0
31 71 PT0_DATA1 B1 RW F1
32 72 PT0_DATA0 B2 RW F2
33 73 PT1_CFG B3 RW F3
34 74 PT1_DATA1 B4 RW F4
35 75 PT1_DATA0 B5 RW F5
36 76 PT2_CFG B6 RW F6
37 77 PT2_DATA1 B7 RW CPU_F F7 RL
38 78 PT2_DATA0 B8 RW F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD FD
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Gray fields are reserved and should not be accessed. # Access is bit specific.
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