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CY8C24123
CY8C24223, CY8C24423
Document Number: 38-12011 Rev. *G Page 28 of 43
Figure 12. PLL Lock Timing Diagram
Figure 13. PLL Lock for Low Gain Setting Timing Diagram
Figure 14. External Crystal Oscillator Startup Timing Diagram
Figure 15. 24 MHz Period Jitter (IMO) Timing Diagram
Figure 16. 32 kHz Period Jitter (ECO) Timing Diagram
24 MHz
F
PLL
PLL
Enable
T
PLLSLEW
PLL
Gain
0
24 MHz
F
PLL
PLL
Enable
T
PLLSLEWLOW
PLL
Gain
1
32 kHz
F
32K2
32K
Select
T
OS
Jitter24M1
F
24M
Jitter32k
F
32K2
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