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EM78P458/459
OTP ROM
R0
R1 (TCC)
R2 (PC)
R3 (Status)
R4 (RSR)
R5 (Port 5)
R6 (Port 6)
R7
R9 (ADCON)
RA (ADDATA)
RB (TMR1L)
RC (TMR1H)
RD (TMR2L)
RE (TMR2H)
RF
16x8
Common
Register
00
01
02
03
04
05
07
06
08
0A
09
0B
0C
0D
0E
0F
11
10
1E
1F
3F
20
21
STACK 4
STACK 3
STACK 2
STACK 1
STACK 0
R8
00
32x8
Bank
Register
(Bank 0)
01
32x8
Bank
Register
(Bank 1)
IOCD0
IOC50
IOC60
IOCE0
IOCF0
STACK 5
STACK 6
STACK 7
20
20
3F
3F
R9<5> (IOCS)
0
IOCC0
IOCB0
IOC90 (GCON)
1
IOC61 (DT1L)
IOC51 (PWMCON)
IOC71 (DT1H)
IOC91 (DT2L)
IOCA1 (DT2H)
IOC81 (PRD1)
IOCB1 (PRD2)
IOCD1 (DL1H)
IOCE1 (DL2L)
IOCF1 (DL2H)
IOCC1 (DL1L)
IOCA0 (AD-CMPCON)
PSR7, PSR6
Fig. 4 Data Memory Configuration
This specification is subject to change without prior notice. 07.01.2003 (V1.3)
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