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EM78P458/459
OTP ROM
M
U
X
PORT
PCWR
PDWR
IOD
PDRD
0
1
PCRD
D
D
Q
Q
Q
Q
_
_
C
L
C
L
P
R
CLK
CLK
NOTE: Pull-down is not shown in the figure.
Fig. 6 The Ccircuit of I/O Port and I/O Control Register for Port 5
PCRD
M
U
X
IOD
0
1
INT
PDRD
P50, /INT
Bit 6 of IOCE0
PCWR
DQ
Q
_
CLK
P
R
C
L
PDWR
DQ
Q
_
CLK
P
R
C
L
P
R
C
L
CLK
DQ
Q
_
P
R
C
L
CLK
DQ
Q
_
PORT
TI 0
NOTE: Pull-high (down) and Open-drain are not shown in the figure.
Fig. 7 The Circuit of I/O Port and I/O Control Register for P50(/INT)
This specification is subject to change without prior notice. 07.01.2003 (V1.3)
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