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EM78P458/459
OTP ROM
When the A/D conversion is complete, the result is loaded to the ADDATA. The START/END bit is
clear, and the ADIF is set.
3. A/D Sampling Time
The accuracy, linearity, and speed of the successive approximation A/D converter are dependent on
the properties of the ADC and the comparator. The source impedance and the internal sampling
impedance directly affect the time required to charge the sample holding capacitor. The application
program controls the length of the sample time to meet the specified accuracy. Generally speaking,
the program should wait for 1 μs for each KΩ of the analog source impedance and at least 1 μs for
the low-impedance source. After the analog input channel is selected, this acquisition time must be
done before the conversion can be started.
4. A/D Conversion Time
CKR0 and CKR1 select the conversion time (Tct), in terms of instruction cycles. This allows the MCU
to run at the maximum frequency without sacrificing the accuracy of A/D conversion. For the
EM78P458/459, the conversion time per bit is about 4μs. Table 8 shows the relationship between
Tct and the maximum operating frequencies.
Table 9 Tct vs. the Maximum Operation Frequency
CKR0:CKR1 Operation Mode Max. operation frequency
00 Fsco/4 1 MHz
01 Fsco/16 4 MHz
10 Fsco/64 16MHz
11 Internal RC -
5. A/D Operation During Sleep Mode
In order to reduce power consumption, the A/D conversion remains operational during sleep mode,
and is obligated to implement the internal RC clock source mode. As the SLEP instruction is executed,
all the operations of the MCU will stop except for the A/D conversion. The RUN bit will be cleared and
the result will be fed to the ADDATA when the conversion is completed. If the ADIE is enabled, the
device will wake up. Otherwise, the A/D conversion will be shut off, no matter what the status of
ADPD bit is.
6. Programming Steps/Considerations
1. Programming steps
Follow these steps to obtain data from the ADC:
This specification is subject to change without prior notice. 07.01.2003 (V1.3)
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