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GEH-6385 Reference and Troubleshooting, 2300 V Drives Chapter 3 Paramters/Functions
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3-35
Function description
The product completely handles configuration of the Frame Phaselock Loop
function. Appropriate user selections of Network interface activate the function, and
user specification of LAN frame time sets the nominal period.
The Boolean variable Frame PLL OK status indicates the status of the Frame
Phaselock Loop. The asserted state indicates that the function has been activated and
that lock status has been validated. The unasserted state indicates that the function is
not activated or that lock status is not validated.
The FPLL Phase error signal reflects the phase error when valid phase information
has been extracted from the interface. A signal value of zero indicates either zero
phase error or invalid phase information. Scaling is such that one per-unit phase error
represents a full communication frame period.
The FPLL Freq Output signal is the frequency adjustment output of the function; the
authority of the function to modify away from nominal frequency is strictly limited.
When the function is not activated, the FPLL Freq Output signal is zero. When the
function is activated but no valid phase information is detected, then FPLL Freq
Output maintains its last valid calculated value.
When phaselock is achieved, Frame PLL OK status is asserted, FPLL Phase error is
at a zero-mean steady-state value, and FPLL Freq Output is at a non-zero, but very
small, steady-state value. When the Frame Phaselock Loop has been requested by
configuration but phaselock is not achieved, then Frame PLL not OK is shown.
LAN Configuration and Health
The following information describes the configuration of the primary signal interface
between the Innovation Series device and the application layer interface. The
application layer may consist of an embedded ACL card, a direct LAN interface
card, or an application-level ISBus serial bus.