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Programming Release Notes
5.25 HP MACRO for OpenVMS
Table 5–1 (Cont.) Macro-32 New Built-ins
Built-in Operands
1
Description
Supported
on
All the _FAULT_variants of
the LFETCH built-in
Generates ’lfetch’ instructions with the
’fault’ completer. For example, IA64_
LFETCH_FAULT_EXCL_NT1
Integrity
servers
1
The built-in requires the operands, where WQ - Write Quadword, PQ - Read Quadword, AB - Address of Byte.
For additional information about underlying instructions, see the respective
hardware architecture manuals.
5.25.2 HP MACRO for OpenVMS Integrity servers
V8.3
The following notes pertain to the HP MACRO for OpenVMS Integrity servers
compiler:
• Prior to OpenVMS Version 8.3, the compiler generated the wrong code for the
HALT instruction. On Integrity servers, the HALT instruction is implemented
using the Itanium
break
instruction with a reserved literal value of
BREAK$C_SYS_HALT
. Because of a bug in the compiler’s build environment,
the Macro-32 compiler used the wrong literal value. This problem has been
fixed in Version 8.3. Any code that uses the HALT instruction should be
recompiled with the Version 8.3 compiler. For systems prior to Version 8.3,
the correct behavior can be accomplished as follows:
$BREAKDEF
IA64_HALT #BREAK$C_SYS_HALT ; Issue break instruction with correct literal
HALT ; Use HALT built-in to inform compiler that this ends the flow of control
• The compiler might optimize away instructions prior to
HALT
,
BPT
, and
EVAX_BUGCHK
. The optimizer does not identify these special instructions as
implicitly reading all registers by either writing a dump file or transferring
control to a debug environment. The apparently unused instructions are
removed by mistake. The compiler has to be taught about the special
behavior of these instructions. Though there is no syntax to force arbitrary
instructions to be included in the final object file, the IA64_LD8_A built-in
can be used as a workaround. See the following Macro-32 paragraphs for
information about this built-in. In addition, specifying
/NOOPTIMIZE
preserves
the apparently unused instructions at the expense of slower and larger code.
• The compiler might optimize away apparently unused memory loads. The
compiler’s optimizer can recognize whether or not the result of a memory
load is used. If the result appears to be unused, the optimizer removes
the memory load as well. However, some code might be using the memory
load to fault a page into memory before raising IPL for example. In these
cases, the removed instruction prevents the page from being faulted into
memory, and the subsequent code at high IPL experiences a fatal page
fault at high IPL exception. Although there is no syntax to force arbitrary
instructions to be included in the final object file, the IA64_LD8_A built-in
can be used as a workaround. The IA64_LD8_A built-in, new in Version 8.3,
generates a special form of the Itanium "ld8" instruction that also places the
fetched address into the ALAT (Advanced Load Address Table). The compiler
identifies this special form of "ld8" as having a side effect and that it cannot
be removed from the final object file even if the result appears to be unused.
The insertion of the address into the ALAT does not cause any problems or
Programming Release Notes 5–21