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Interlocked Memory Instructions (Alpha Only)
A.4 Coding Requirements
To correct this code, the memory access to read the value of INDEX must first
be moved outside the LDQ_L/STQ_C sequence. Next, the branch between the
LDQ_L and STQ_C, to the label IS_CLEAR, must be eliminated. In this case,
it could be done using a CMOVEQ instruction. The CMOVxx instructions are
frequently useful for eliminating branches around simple value moves. The
following example shows the corrected code:
movl index, r2 ; Get the current index
getlck: evax_ldql r0, lockdata(r8) ; and then the lock data.
evax_cmoveq r0, r3, r2 ; If zero, use special index.
incl r0 ; Increment lock count
evax_stqc r0, lockdata(r8) ; and store it.
tstl r0 ; Did write succeed?
beql getlck ; Retry if not.
A.5 Compiler Versions
Table A–1 contains information about versions of compilers that might generate
noncompliant code sequences and the recommended minimum versions to use
when you recompile.
Table A–1 Versions of OpenVMS Compilers
Old Version Recommended Minimum Version
BLISS V1.1 BLISS V1.3
DEC Ada V3.5 HP Ada V3.5A
DEC C V5.x DEC C V6.0
DEC C++ V5.x DEC C++ V6.0
DEC COBOL V2.4, V2.5, V2.6 COBOL V2.8
DEC Pascal V5.0-2 DEC Pascal V5.1-11
MACRO–32 V3.0 V3.1 for OpenVMS Version 7.1-2
V4.1 for OpenVMS Version 7.2
MACRO–64 V1.2 See below.
Current versions of the MACRO–64 assembler might still encounter the loop
rotation issue. However, MACRO–64 does not perform code optimization by
default, and this problem occurs only when optimization is enabled. If SRM_
CHECK indicates a noncompliant sequence in the MACRO–64 code, it should
first be recompiled without optimization. If the sequence is still flagged when
retested, the source code itself contains a noncompliant sequence that must be
corrected.
Alpha computers with 21264 processors require strict adherence to the
restrictions for interlocked memory sequences for the LDx_L and STx_C
instructions described in the Alpha Architecture Reference Manual, Third Edition.
To help ensure that uses of interlocked memory instructions conform to the
architectural guidelines, additional checking has been added to Version 3.1 of the
MACRO–32 Compiler for OpenVMS Alpha.
The Alpha Architecture Reference Manual, Third Edition describes the rules
for instruction use within interlocked memory sequences in Section 4.2.4. The
MACRO–32 for OpenVMS Alpha Version 3.1 compiler observes these rules in the
code it generates from MACRO–32 source code. However, the compiler provides
EVAX_LQxL and EVAX_STxC built-ins, which allow these instructions to be
written directly in source code.
Interlocked Memory Instructions (Alpha Only) A–5