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www.hitachi.com BladeSymphony 1000 Architecture White Paper 11
The Intel Itanium is optimized for dual processor-based platforms and clusters and includes the
following features:
• Wide, parallel hardware based on Itanium architecture for high performance
– Integrated on-die cache of up to 24 MB, cache hints for L1, L2, and L3 caches for reduced
memory latency
– 128 general and 128 floating-point registers supporting register rotation
– Register stack engine for effective management of processor resources
– Support for predication and speculation
• Extensive RAS features for business-critical applications
– Full SMBus compatibility
– Enhanced machine check architecture with extensive ECC and parity protection
– Enhanced thermal management
– Built-in processor information ROM (PIROM)
– Built-in programmable EEPROM
– Socket Level Lockstep
– Core Level Lockstep
• High bandwidth system bus for multiprocessor scalability
– 6.4 GB/sec. bandwidth
– 28-bit wide data bus
– 400 MHz and 533 data bus frequency
– 50-bits of physical memory addressing and 64-bits of virtual addressing
• Two complete 64-bit processing cores on one chip running at 104W
Cache
The processor supports up to 24 MB (12 MB per core) of low-latency, on-die L3 cache (14 cycles)
providing 102 GB/sec. aggregate bandwidth to the processor cores. It also include separate 16 KB
Instruction L1 and 16 KB Data L1 cache per core, as well as separate 1 MB Instruction L2 and 256 KB
Data L2 cache per core for higher speed and lower latency memory access.
Hyper-Threading Technology
Hyper-Threading Technology (HT Technology) enables one physical processor to transparently appear
and behave as two virtual processors to the operating system. With HT Technology, one dual-core
processor is able to simultaneously run four software threads. HT Technology provides thread-level
parallelism on each processor, resulting in more efficient use of processor resources, higher processing
throughput, and improved performance on multi threaded software, as well as increasing the number of
users a server can support. In order to leverage HT Technology, SMP support in the operating system is
required.
Intel Cache Safe Technology and Enhanced Machine Check Architecture
Intel Cache Safe Technology is an automatic cache recovery capability that allows the processor and
server to continue normal operation in case of cache error. It automatically disables cache lines in the
event of a cache memory error, providing higher levels of uptime.